Add Mindspeed Comcerto platform support

gistfile1.txt

[PATCH 1/3] Add Mindspeed Comcerto platform support
stanleymiao at gmail.com stanleymiao at gmail.com
Thu Oct 14 04:38:07 EDT 2010

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From: Stanley.Miao <stanley.miao at windriver.com>

Add Mindspeed Comcerto platform support. Now this patch includes only
Multifunction EVM board with Comcerto-1000 CPU.

Signed-off-by: Stanley.Miao <stanley.miao at windriver.com>
---
 arch/arm/Kconfig                                   |   11 ++
 arch/arm/Makefile                                  |    1 +
 arch/arm/boot/compressed/Makefile                  |    4 +
 arch/arm/boot/compressed/head-comcerto.S           |    6 +
 arch/arm/boot/compressed/head.S                    |    5 +
 arch/arm/mach-comcerto/Kconfig                     |   32 +++++
 arch/arm/mach-comcerto/Makefile                    |   10 ++
 arch/arm/mach-comcerto/Makefile.boot               |    2 +
 arch/arm/mach-comcerto/board-c1kmfcn_evm.c         |   88 ++++++++++++
 arch/arm/mach-comcerto/comcerto-1000.c             |  146 ++++++++++++++++++++
 .../arm/mach-comcerto/include/mach/comcerto-1000.h |   91 ++++++++++++
 arch/arm/mach-comcerto/include/mach/debug-macro.S  |   46 ++++++
 arch/arm/mach-comcerto/include/mach/entry-macro.S  |   70 ++++++++++
 arch/arm/mach-comcerto/include/mach/hardware.h     |   37 +++++
 arch/arm/mach-comcerto/include/mach/io.h           |   32 +++++
 arch/arm/mach-comcerto/include/mach/memory.h       |   33 +++++
 arch/arm/mach-comcerto/include/mach/system.h       |   39 +++++
 arch/arm/mach-comcerto/include/mach/timex.h        |   28 ++++
 arch/arm/mach-comcerto/include/mach/uncompress.h   |   58 ++++++++
 arch/arm/mach-comcerto/include/mach/vmalloc.h      |   21 +++
 20 files changed, 760 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/compressed/head-comcerto.S
 create mode 100644 arch/arm/mach-comcerto/Kconfig
 create mode 100644 arch/arm/mach-comcerto/Makefile
 create mode 100644 arch/arm/mach-comcerto/Makefile.boot
 create mode 100644 arch/arm/mach-comcerto/board-c1kmfcn_evm.c
 create mode 100644 arch/arm/mach-comcerto/comcerto-1000.c
 create mode 100644 arch/arm/mach-comcerto/include/mach/comcerto-1000.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-comcerto/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-comcerto/include/mach/hardware.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/io.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/memory.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/system.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/timex.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/vmalloc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 88c97bc..ca6ccf7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -334,6 +334,15 @@ config ARCH_EP93XX
 	help
 	  This enables support for the Cirrus EP93xx series of CPUs.
 
+config ARCH_COMCERTO
+	bool "Mindspeed Comcerto"
+	select ZONE_DMA
+	select CPU_V6
+	help
+	  This enables support for Mindspeed's Comcerto development boards.
+	  If you would like to build your kernel to run on one of these boards
+	  then you must say 'Y' here. Otherwise say 'N'
+
 config ARCH_FOOTBRIDGE
 	bool "FootBridge"
 	select CPU_SA110
@@ -841,6 +850,8 @@ source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
 
+source "arch/arm/mach-comcerto/Kconfig"
+
 source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-dove/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 59c1ce8..2daad67 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -141,6 +141,7 @@ machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
 machine-$(CONFIG_ARCH_IOP33X)		:= iop33x
+machine-$(CONFIG_ARCH_COMCERTO)	:= comcerto
 machine-$(CONFIG_ARCH_IXP2000)		:= ixp2000
 machine-$(CONFIG_ARCH_IXP23XX)		:= ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)		:= ixp4xx
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 65a7c1c..e8419db 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -33,6 +33,10 @@ ifeq ($(CONFIG_CPU_XSCALE),y)
 OBJS		+= head-xscale.o
 endif
 
+ifeq ($(CONFIG_ARCH_COMCERTO),y)
+OBJS		+= head-comcerto.o
+endif
+
 ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y)
 OBJS		+= head-sharpsl.o
 endif
diff --git a/arch/arm/boot/compressed/head-comcerto.S b/arch/arm/boot/compressed/head-comcerto.S
new file mode 100644
index 0000000..60160f6
--- /dev/null
+++ b/arch/arm/boot/compressed/head-comcerto.S
@@ -0,0 +1,6 @@
+#include <asm/mach-types.h>
+
+	.section	".start", "ax"
+	ldr	r7, mach_type
+
+mach_type:     .word    MACH_TYPE_COMCERTO
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 6825c34..8f38fbf 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -66,6 +66,11 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 		add	\rb, \rb, #0x00010000	@ Ser1
 #endif
 		.endm
+#elif defined(CONFIG_ARCH_COMCERTO)
+		.macro  loadsp, rb, tmp
+		mov     \rb, #0x10000000
+		orr     \rb, \rb, #0x00090000
+		.endm
 #elif defined(CONFIG_ARCH_S3C2410)
 		.macro loadsp, rb, tmp
 		mov	\rb, #0x50000000
diff --git a/arch/arm/mach-comcerto/Kconfig b/arch/arm/mach-comcerto/Kconfig
new file mode 100644
index 0000000..a61a31a
--- /dev/null
+++ b/arch/arm/mach-comcerto/Kconfig
@@ -0,0 +1,32 @@
+if ARCH_COMCERTO
+
+menu "Comcerto Implementation Options"
+
+choice
+	prompt "Comcerto System Type"
+	default ARCH_M83XXX
+
+config ARCH_M83XXX
+	bool "M83xxx"
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+	help
+	  Say Y here if you intend to run this kernel with a Comcerto1000 device.
+
+endchoice
+
+choice
+	prompt "Comcerto Board type"
+	default EVM_C1KMFCN_EVM
+
+config EVM_C1KMFCN_EVM
+	bool "C1KMFCN_EVM"
+	depends on ARCH_M83XXX
+	help
+	  Say Y here if you intend to run this kernel with a C1K Multifunction EVM board.
+
+endchoice
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-comcerto/Makefile b/arch/arm/mach-comcerto/Makefile
new file mode 100644
index 0000000..70aac61
--- /dev/null
+++ b/arch/arm/mach-comcerto/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y :=
+
+obj-$(CONFIG_ARCH_M83XXX)			+= comcerto-1000.o
+obj-$(CONFIG_EVM_C1KMFCN_EVM)			+= board-c1kmfcn_evm.o
diff --git a/arch/arm/mach-comcerto/Makefile.boot b/arch/arm/mach-comcerto/Makefile.boot
new file mode 100644
index 0000000..6262c4b
--- /dev/null
+++ b/arch/arm/mach-comcerto/Makefile.boot
@@ -0,0 +1,2 @@
+zreladdr-y     := 0x80808000
+params_phys-y  := 0x80800100
diff --git a/arch/arm/mach-comcerto/board-c1kmfcn_evm.c b/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
new file mode 100644
index 0000000..74a7da3
--- /dev/null
+++ b/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
@@ -0,0 +1,88 @@
+/*
+ * linux/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
+ *
+ *  Copyright (C) 2004,2008 Mindspeed Technologies, Inc.
+ *  Copyright (c) 2010 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/device.h>
+#include <linux/serial_8250.h>
+#include <asm/sizes.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/mach/arch.h>
+#include <mach/hardware.h>
+
+/* --------------------------------------------------------------------
+ *  Serial interface
+ * -------------------------------------------------------------------- */
+static struct plat_serial8250_port comcerto_uart_data[] = {
+	{
+		.mapbase	= COMCERTO_APB_UART0_BASE,
+		.membase	= (void *)APB_VADDR(COMCERTO_APB_UART0_BASE),
+		.irq		= IRQ_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= COMCERTO_DEFAULTAHBCLK * 1000000,
+	},
+	{
+		.flags		= 0,
+	},
+};
+
+static struct platform_device comcerto_uart = {
+	.name	= "serial8250",
+	.id	= PLAT8250_DEV_PLATFORM,
+	.dev	= {
+		.platform_data	= comcerto_uart_data,
+	},
+};
+
+static struct platform_device *comcerto_devices[] __initdata = {
+	&comcerto_uart,
+};
+
+/************************************************************************
+ *  Machine definition
+ *
+ ************************************************************************/
+static void __init platform_map_io(void)
+{
+	device_map_io();
+}
+
+static void __init platform_irq_init(void)
+{
+}
+
+static void __init platform_init(void)
+{
+	platform_add_devices(comcerto_devices, ARRAY_SIZE(comcerto_devices));
+}
+
+MACHINE_START(COMCERTO, "Comcerto 1000 (Multifunction EVM)")
+	/* Mindspeed Technologies Inc. */
+	.phys_io	= COMCERTO_AHB_APB_BASE,
+	.io_pg_offst	= ((COMCERTO_AHB_APB_BASE) >> 18) & 0xfffc,
+	.boot_params	= COMCERTO_SDRAM_BASE + 0x100,
+	.map_io		= platform_map_io,
+	.init_irq	= platform_irq_init,
+	.init_machine	= platform_init,
+	.timer		= &comcerto_timer,
+MACHINE_END
diff --git a/arch/arm/mach-comcerto/comcerto-1000.c b/arch/arm/mach-comcerto/comcerto-1000.c
new file mode 100644
index 0000000..09032ea
--- /dev/null
+++ b/arch/arm/mach-comcerto/comcerto-1000.c
@@ -0,0 +1,146 @@
+/*
+ *  linux/arch/arm/mach-comcerto/comcerto-1000.c
+ *
+ *  Copyright (C) 2004,2008 Mindspeed Technologies, Inc.
+ *  Copyright (c) 2010 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+/***********************************************************
+ *   Virtual address Mapping                               *
+ *                                                         *
+ ***********************************************************/
+
+static struct map_desc comcerto_io_desc[] __initdata = {
+	{
+		.virtual    = SDRAM_MSP_MEMORY_VADDR,
+		.pfn        = __phys_to_pfn(SDRAM_MSP_MEMORY_PHY),
+		.length     = SDRAM_MSP_MEMORY_SIZE,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = ARAM_MEMORY_VADDR,
+		.pfn        = __phys_to_pfn(COMCERTO_AHB_ARAM_BASE),
+		.length     = ARAM_MEMORY_SIZE,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = (ARAM_MEMORY_VADDR + 0x100000),
+		.pfn        = __phys_to_pfn(COMCERTO_AHB_ARAM_BASE + 0x100000),
+		.length     = ARAM_MEMORY_SIZE,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = ARAM_MEMORY_VADDR + 0x100000,
+		.pfn        = __phys_to_pfn(COMCERTO_AHB_ARAM_BASE + 0x100000),
+		.length     = ARAM_MEMORY_SIZE,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_TIMER_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_TIMER_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_GPIO_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_GPIO_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_UART0_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_UART0_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_UART1_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_UART1_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_SPI_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_SPI_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_I2C_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_I2C_BASE),
+		.length     = SZ_16K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_INTC_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_INTC_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_CLK_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_CLK_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_EMAC0_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_EMAC0_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_EMAC1_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_EMAC1_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_ARAM_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_ARAM_BASE),
+		.length     = SZ_4K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = APB_VADDR(COMCERTO_APB_EXPBUS_BASE),
+		.pfn        = __phys_to_pfn(COMCERTO_APB_EXPBUS_BASE),
+		.length     = SZ_64K,
+		.type       = MT_DEVICE
+	},
+	{
+		.virtual    = COMCERTO_IPSEC_VADDR_BASE,
+		.pfn        = __phys_to_pfn(COMCERTO_AHB_IPSEC_BASE),
+		.length     = SZ_1M,
+		.type       = MT_DEVICE
+	},
+};
+
+void __init device_map_io(void)
+{
+	iotable_init(comcerto_io_desc, ARRAY_SIZE(comcerto_io_desc));
+}
+
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
new file mode 100644
index 0000000..f48ae34
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
@@ -0,0 +1,91 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/comcerto-1000.h
+ *
+ *  Copyright (C) 2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_COMCERTO1000_H__
+#define __ASM_ARCH_COMCERTO1000_H__
+
+#define COMCERTO_DEFAULTAHBCLK          187 /* MHz */
+#define COMCERTO_PHYCLK			250 /* MHz */
+#define COMCERTO_ARMCLK			650 /* MHz */
+
+/***** Physical address of IO on APB Bus *****/
+
+/*	0x001F0000 Reserved*/
+#define COMCERTO_APB_MDMA_BASE			0x101E0000
+#define COMCERTO_APB_TDMA2_BASE			0x101D0000
+/*	0x101B0000 --> 0x101C0000 Reserved*/
+#define COMCERTO_APB_EXPBUS_BASE		0x101A0000
+#define COMCERTO_APB_EMAC1_BASE			0x10190000
+/*	0x10100000 --> 0x00180000 Reserved*/
+#define COMCERTO_APB_ARAM_BASE			0x100F0000
+/*	0x100E0000 Reserved*/
+#define COMCERTO_APB_EMAC0_BASE			0x100D0000
+/*	0x100C0000 Reserved*/
+#define COMCERTO_APB_CLK_BASE			0x100B0000
+#define COMCERTO_APB_INTC_BASE			0x100A0000
+#define COMCERTO_APB_I2C_BASE			0x1009C000
+#define COMCERTO_APB_SPI_BASE			0x10098000
+#define COMCERTO_APB_UART1_BASE			0x10094000
+#define COMCERTO_APB_UART0_BASE			0x10090000
+/*	0x10080000 Reserved*/
+#define COMCERTO_APB_GPIO_BASE			0x10070000
+#define COMCERTO_APB_PCIePHY_BASE		0x10060000
+#define COMCERTO_APB_TIMER_BASE			0x10050000
+#define COMCERTO_APB_AHB_BASE			0x10040000
+#define COMCERTO_APB_PCIe1_BASE			0x10030000
+#define COMCERTO_APB_TDMA_BASE			0x10020000
+#define COMCERTO_APB_PCIe0_BASE			0x10010000
+#define COMCERTO_APB_TDM_BASE			0x10000000
+
+/***** Physical address on AHB Bus *****/
+#define COMCERTO_AHB_HIGHMEMDDR_BASE		0xFFFF0000
+#define COMCERTO_AHB_DDR_BASE			0x80000000
+#define COMCERTO_AHB_PCIe1_BASE			0x50000000
+#define COMCERTO_AHB_PCIe0_BASE			0x40000000
+#define COMCERTO_AHB_EXP_BASE			0x20000000
+#define COMCERTO_AHB_PCIe1CMD_BASE		0x11410000
+#define COMCERTO_AHB_PCIe0CMD_BASE		0x11400000
+#define COMCERTO_AHB_IBR_BASE			0x11000000
+#define COMCERTO_AHB_APB_BASE			0x10000000
+#define COMCERTO_AHB_USB0_BASE			0x0F000000
+#define COMCERTO_AHB_IPSEC_BASE			0x0E000000
+#define COMCERTO_AHB_DDRCONFIG_BASE		0x0D000000
+#define COMCERTO_AHB_ARAM_BASE			0x0A000000
+
+/* Physical addresses of memories */
+#define COMCERTO_SDRAM_BASE                     (COMCERTO_AHB_DDR_BASE + SZ_8M)
+#define ARAM_MEMORY_SIZE                        SZ_128K
+#define SDRAM_MSP_MEMORY_PHY                    COMCERTO_AHB_DDR_BASE
+#define SDRAM_MSP_MEMORY_SIZE                   SZ_8M
+
+#define IO_SPACE_LIMIT                          0
+
+/*
+ * Virtual address mapping
+ */
+#define SDRAM_MSP_MEMORY_VADDR		0xf0000000
+#define ARAM_MEMORY_VADDR		0xfa000000
+#define COMCERTO_PCIe0CMD_VADDR_BASE	0xfa020000
+#define COMCERTO_PCIe1CMD_VADDR_BASE	0xfa030000
+#define COMCERTO_IPSEC_VADDR_BASE	0xfb000000
+#define APB_VADDR_BASE			0xfc000000	/* VA of IO on APB bus */
+
+#define APB_VADDR(x)            ((x) - COMCERTO_AHB_APB_BASE + APB_VADDR_BASE)
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/debug-macro.S b/arch/arm/mach-comcerto/include/mach/debug-macro.S
new file mode 100644
index 0000000..42bc5a0
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/debug-macro.S
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/debug-macro.S
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define UART_LSR	0x14
+
+	.macro	addruart,rx, tmp
+	mrc	p15, 0, \rx, c1, c0
+	tst	\rx, #1			@ MMU enabled?
+	moveq	\rx, #0x10000000	@ physical base address
+	movne	\rx, #0xfc000000	@ virtual base
+	orr	\rx, \rx, #0x00090000	@ UART0
+	.endm
+
+	.macro	senduart,rd,rx
+	strb	\rd, [\rx, #0x00]
+	.endm
+
+	.macro	waituart,rd,rx
+1001:	ldrb	\rd, [\rx, #UART_LSR]
+	tst	\rd, #0x20		@ wait for THRE
+	beq	1001b
+	.endm
+
+	.macro	busyuart,rd,rx
+1001:	ldrb	\rd, [\rx, #UART_LSR]
+	and	\rd, \rd, #0x60
+	teq	\rd, #0x60		@ wait for TEMT and THRE
+	bne	1001b
+	.endm
diff --git a/arch/arm/mach-comcerto/include/mach/entry-macro.S b/arch/arm/mach-comcerto/include/mach/entry-macro.S
new file mode 100644
index 0000000..442ad92
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/entry-macro.S
@@ -0,0 +1,70 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/entry-macro.S
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <mach/hardware.h>
+
+#if defined(CONFIG_ARCH_COMCERTO)
+		.macro	disable_fiq
+		.endm
+
+		.macro  get_irqnr_preamble, base, tmp
+		.endm
+
+		.macro  arch_ret_to_user, tmp1, tmp2
+		.endm
+
+		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		mov	\irqnr, #0
+		ldr	\base, =COMCERTO_INTC_CSP_IRQ_WNR
+		ldr	\tmp, [\base]
+		cmp	\tmp, #0
+		beq	10011f
+		cmp	\tmp, #32
+		movne	\irqnr, \tmp
+		bne	1004f
+
+
+10011:
+		mov	\irqnr, #0
+		ldr	\base, =COMCERTO_INTC_STATUS_REG_1
+		ldr	\tmp, =COMCERTO_INTC_CSP_IRQMASK_1
+		ldr	\irqstat, [\base]
+		ldr	\tmp, [\tmp]
+		ands	\irqstat, \irqstat, \tmp
+		beq	1004f
+
+		tst 	\irqstat, #0x2000
+		movne	\irqnr,#13
+		bne	1003f
+
+1001:	tst	\irqstat, #1
+		bne	1003f
+		add	\irqnr, \irqnr, #1
+		mov	\irqstat, \irqstat, lsr #1
+		cmp	\irqnr, #32
+		bcc	1001b
+1003:		add	\irqnr, \irqnr, #32
+
+1004:
+		.endm
+
+                .macro  irq_prio_table
+                .endm
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/hardware.h b/arch/arm/mach-comcerto/include/mach/hardware.h
new file mode 100644
index 0000000..577289d
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/hardware.h
@@ -0,0 +1,37 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/hardware.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/***** Device *****/
+#if defined(CONFIG_ARCH_M83XXX)
+	#include <mach/comcerto-1000.h>
+#else
+	#error "mach/hardware.h :  Unknown architecture"
+#endif
+
+#ifndef __ASSEMBLY__
+struct sys_timer;
+extern struct sys_timer comcerto_timer;
+extern void device_map_io(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/io.h b/arch/arm/mach-comcerto/include/mach/io.h
new file mode 100644
index 0000000..be3320f
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/io.h
@@ -0,0 +1,32 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/io.h
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_COMCERTO1000_IO_H
+#define __ASM_ARCH_COMCERTO1000_IO_H
+
+#include <asm/io.h>
+
+#if !defined(CONFIG_PCI)
+
+#define __io(a)		((void __iomem *)(a))
+#define __mem_pci(a)	(a)
+
+#endif
+
+#endif /* __ASM_ARCH_COMCERTO1000_IO_H */
diff --git a/arch/arm/mach-comcerto/include/mach/memory.h b/arch/arm/mach-comcerto/include/mach/memory.h
new file mode 100644
index 0000000..6d42d06
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/memory.h
@@ -0,0 +1,33 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/memory.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <mach/hardware.h>
+
+#define PHYS_OFFSET		COMCERTO_SDRAM_BASE
+
+#define __virt_to_bus(x)	__virt_to_phys(x)
+#define __bus_to_virt(x)	__phys_to_virt(x)
+#define __pfn_to_bus(x)		__pfn_to_phys(x)
+#define __bus_to_pfn(x)		__phys_to_pfn(x)
+
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/system.h b/arch/arm/mach-comcerto/include/mach/system.h
new file mode 100644
index 0000000..364cc7e
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/system.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/system.h
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+	/*
+	 * This should do all the clock switching
+	 * and wait for interrupt tricks
+	 */
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-comcerto/include/mach/timex.h b/arch/arm/mach-comcerto/include/mach/timex.h
new file mode 100644
index 0000000..4ca125d
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/timex.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/timex.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H__
+#define __ASM_ARCH_TIMEX_H__
+
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE		(COMCERTO_DEFAULTAHBCLK * 1000 * 1000)
+
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/uncompress.h b/arch/arm/mach-comcerto/include/mach/uncompress.h
new file mode 100644
index 0000000..e3e6938
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/uncompress.h
@@ -0,0 +1,58 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2004,2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#define UART_DR		(*(volatile unsigned long *)0x10090000)
+#define UART_LSR	(*(volatile unsigned long *)0x10090014)
+
+static inline void putc(int c)
+{
+	while (!(UART_LSR & 0x20))
+		barrier();
+
+	UART_DR = c;
+}
+
+static void flush(void)
+{
+}
+static inline void puts(const char *ptr)
+{
+	char c;
+
+	while ((c = *ptr++) != '\0') {
+		if (c == '\n')
+			putc('\r');
+		putc(c);
+	}
+
+	flush();
+
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-comcerto/include/mach/vmalloc.h b/arch/arm/mach-comcerto/include/mach/vmalloc.h
new file mode 100644
index 0000000..f807501
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define VMALLOC_END       (0xF0000000)
-- 
1.5.4.3


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gistfile2.txt

[PATCH 2/3] Add hardware timer support for Mindspeed Comcerto platflorm
stanleymiao at gmail.com stanleymiao at gmail.com
Thu Oct 14 04:38:08 EDT 2010

    Previous message: Add Mindspeed Comcerto platform support
    Next message: [PATCH 3/3] Add irqs definition and handler for Mindspeed Comcerto platform
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From: Stanley.Miao <stanley.miao at windriver.com>

Add hardware timer support for Comcerto platflorm. Timer0 is used by MSP
and timer2 is used by fpp, so we choose timer1 for clockevent and timer3 for
clocksource.

Signed-off-by: Stanley.Miao <stanley.miao at windriver.com>
---
 arch/arm/mach-comcerto/Makefile                    |    2 +-
 .../arm/mach-comcerto/include/mach/comcerto-1000.h |    3 +
 .../include/mach/comcerto-1000/timer.h             |   62 ++++++
 arch/arm/mach-comcerto/include/mach/system.h       |    3 +
 arch/arm/mach-comcerto/time.c                      |  227 ++++++++++++++++++++
 5 files changed, 296 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-comcerto/include/mach/comcerto-1000/timer.h
 create mode 100644 arch/arm/mach-comcerto/time.c

diff --git a/arch/arm/mach-comcerto/Makefile b/arch/arm/mach-comcerto/Makefile
index 70aac61..c514d20 100644
--- a/arch/arm/mach-comcerto/Makefile
+++ b/arch/arm/mach-comcerto/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y :=
+obj-y := time.o
 
 obj-$(CONFIG_ARCH_M83XXX)			+= comcerto-1000.o
 obj-$(CONFIG_EVM_C1KMFCN_EVM)			+= board-c1kmfcn_evm.o
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
index f48ae34..10086c4 100644
--- a/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
@@ -88,4 +88,7 @@
 #define APB_VADDR_BASE			0xfc000000	/* VA of IO on APB bus */
 
 #define APB_VADDR(x)            ((x) - COMCERTO_AHB_APB_BASE + APB_VADDR_BASE)
+
+#include <mach/comcerto-1000/timer.h>
+
 #endif
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000/timer.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000/timer.h
new file mode 100644
index 0000000..5372e37
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000/timer.h
@@ -0,0 +1,62 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/comcerto-1000/timer.h
+ *
+ *  Copyright (C) 2004-2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+/* Comcerto Timers  */
+#define COMCERTO_TIMER0_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x00)
+#define COMCERTO_TIMER0_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x04)
+#define COMCERTO_TIMER1_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x08)
+#define COMCERTO_TIMER1_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x0C)
+#define COMCERTO_TIMER1_LOW_BOUND           APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x0C)
+#define COMCERTO_TIMER2_LOW_BOUND           APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x10)
+#define COMCERTO_TIMER2_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x14)
+#define COMCERTO_TIMER2_CTRL                APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x18)
+#define COMCERTO_TIMER2_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x1C)
+#define COMCERTO_TIMER3_LOW_BOUND           APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x20)
+#define COMCERTO_TIMER3_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x24)
+#define COMCERTO_TIMER3_CTRL                APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x28)
+#define COMCERTO_TIMER3_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x2C)
+#define COMCERTO_TIMER4_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x30)
+#define COMCERTO_TIMER4_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x34)
+#define COMCERTO_TIMER5_LOW_BOUND           APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x38)
+#define COMCERTO_TIMER5_HIGH_BOUND          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x3C)
+#define COMCERTO_TIMER5_CURRENT_COUNT       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x40)
+#define COMCERTO_TIMER5_CTRL                APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x44)
+#define COMCERTO_TIMER_IRQ_MASK             APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x48)
+#define COMCERTO_TIMER_STATUS               APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x50)
+#define COMCERTO_TIMER_STATUS_CLR           APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x50)
+#define COMCERTO_TIMER_WDT_HIGH_BOUND       APB_VADDR(COMCERTO_APB_TIMER_BASE + 0xD0)
+#define COMCERTO_TIMER_WDT_CONTROL          APB_VADDR(COMCERTO_APB_TIMER_BASE + 0xD4)
+#define COMCERTO_TIMER_WDT_CURRENT_COUNT    APB_VADDR(COMCERTO_APB_TIMER_BASE + 0xD8)
+
+#define COMCERTO_TIMER_WDT_CONTROL_TIMER_ENABLE		(1 << 0)
+
+/* COMCERTO_TIMER_IRQ_MASK */
+#define COMCERTO_TIMER0     0x01
+#define COMCERTO_TIMER1     0x02
+#define COMCERTO_TIMER2     0x04
+#define COMCERTO_TIMER3     0x08
+#define COMCERTO_TIMER4     0x10
+#define COMCERTO_TIMER5     0x20
+#define COMCERTO_ALL        0xFF
+#define COMCERTO_TIMER_CSP  (COMCERTO_TIMER1 | COMCERTO_TIMER2 | COMCERTO_TIMER3 | COMCERTO_TIMER4 | COMCERTO_TIMER5)
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/system.h b/arch/arm/mach-comcerto/include/mach/system.h
index 364cc7e..d24914d 100644
--- a/arch/arm/mach-comcerto/include/mach/system.h
+++ b/arch/arm/mach-comcerto/include/mach/system.h
@@ -34,6 +34,9 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
+	/* use watch dog timer to reset the board */
+	__raw_writel(0x1, COMCERTO_TIMER_WDT_CONTROL);
+	__raw_writel(0x1, COMCERTO_TIMER_WDT_HIGH_BOUND);
 }
 
 #endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-comcerto/time.c b/arch/arm/mach-comcerto/time.c
new file mode 100644
index 0000000..40e3515
--- /dev/null
+++ b/arch/arm/mach-comcerto/time.c
@@ -0,0 +1,227 @@
+/*
+ * linux/arch/arm/mach-comcerto/time.c
+ *
+ * Copyright (C) 2008 Mindspeed Technologies, Inc.
+ * Copyright (c) 2010 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <asm/mach/time.h>
+
+#define TID_CLOCKEVENT	1
+#define TID_CLOCKSOURCE	3
+
+static DEFINE_SPINLOCK(timer_lock);
+
+struct comcerto_gptimer {
+	char *name;
+	unsigned long id; /* maybe not needed */
+	unsigned long mask;
+	unsigned long hbound;
+	unsigned long lbound;
+	unsigned long count;
+};
+
+static void gptimer_enable(struct comcerto_gptimer *gptimer)
+{
+	unsigned long flags;
+	unsigned long irq_mask;
+
+	spin_lock_irqsave(&timer_lock, flags);
+	irq_mask = __raw_readl(COMCERTO_TIMER_IRQ_MASK);
+	irq_mask |= gptimer->mask;
+	__raw_writel(irq_mask, COMCERTO_TIMER_IRQ_MASK);
+	spin_unlock_irqrestore(&timer_lock, flags);
+}
+
+static void gptimer_disable(struct comcerto_gptimer *gptimer)
+{
+	unsigned long flags;
+	unsigned long irq_mask;
+
+	spin_lock_irqsave(&timer_lock, flags);
+	irq_mask = __raw_readl(COMCERTO_TIMER_IRQ_MASK);
+	irq_mask &= ~gptimer->mask;
+	__raw_writel(irq_mask, COMCERTO_TIMER_IRQ_MASK);
+	spin_unlock_irqrestore(&timer_lock, flags);
+}
+
+static struct comcerto_gptimer timers[] = {
+	[TID_CLOCKEVENT] = {
+		.name	= "timer1",
+		.id	= TID_CLOCKEVENT,
+		.mask	= COMCERTO_TIMER1,
+		.hbound	= COMCERTO_TIMER1_HIGH_BOUND,
+		.lbound = COMCERTO_TIMER1_LOW_BOUND,
+		.count = COMCERTO_TIMER1_CURRENT_COUNT,
+	},
+	[TID_CLOCKSOURCE] = {
+		.name	= "timer3",
+		.id	= TID_CLOCKSOURCE,
+		.mask	= COMCERTO_TIMER3,
+		.hbound	= COMCERTO_TIMER3_HIGH_BOUND,
+		.lbound = COMCERTO_TIMER3_LOW_BOUND,
+		.count = COMCERTO_TIMER3_CURRENT_COUNT,
+	},
+};
+
+static void gptimer_set_bound(struct comcerto_gptimer *gptimer,
+					unsigned low, unsigned high)
+{
+	__raw_writel(high, gptimer->hbound);
+	/* __raw_writel(low, gptimer->lbound); */
+}
+
+static void gptimer_clear_status(struct comcerto_gptimer *gptimer)
+{
+	__raw_writel(gptimer->mask, COMCERTO_TIMER_STATUS_CLR);
+}
+
+static unsigned long gptimer_get_current_count(struct comcerto_gptimer *timer)
+{
+	return __raw_readl(timer->count);
+}
+
+static int comcerto_set_next_event(unsigned long cycles,
+					struct clock_event_device *evt)
+{
+	struct comcerto_gptimer *t = &timers[TID_CLOCKEVENT];
+
+	if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
+		gptimer_enable(t);
+	return 0;
+}
+
+static void comcerto_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	struct comcerto_gptimer *t = &timers[TID_CLOCKEVENT];
+
+	if (mode != CLOCK_EVT_MODE_PERIODIC)
+		gptimer_disable(t);
+	else
+		gptimer_enable(t);
+}
+
+static struct clock_event_device clockevent = {
+	.name           = "clockevent",
+	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.rating         = 200,
+	.shift          = 24,
+	.set_mode       = comcerto_set_mode,
+	.set_next_event = comcerto_set_next_event,
+};
+
+static cycle_t comcerto_timer3_read(struct clocksource *cs)
+{
+	return (cycle_t)gptimer_get_current_count(&timers[TID_CLOCKSOURCE]);
+}
+
+static struct clocksource clocksource = {
+	.name   = "clocksource",
+	.rating = 200,
+	.read   = comcerto_timer3_read,
+	.mask   = CLOCKSOURCE_MASK(32),
+	.shift  = 24,
+	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init comcerto_clocksource_init(void)
+{
+	struct comcerto_gptimer *t = &timers[TID_CLOCKSOURCE];
+
+	gptimer_set_bound(t, 0, 0xffffffff);
+	clocksource.mult = clocksource_hz2mult(COMCERTO_DEFAULTAHBCLK, clocksource.shift);
+	if (clocksource_register(&clocksource))
+		printk(KERN_ERR "%s: can't register clocksource!\n", clocksource.name);
+}
+
+static irqreturn_t comcerto_timer1_interrupt(int irq, void *dev_id)
+{
+	u32 status;
+	struct comcerto_gptimer *t = &timers[TID_CLOCKEVENT];
+	struct clock_event_device *dev = &clockevent;
+
+	status = __raw_readl(COMCERTO_TIMER_STATUS) & __raw_readl(COMCERTO_TIMER_IRQ_MASK);
+
+	/* timer1 expired */
+	if (status & t->mask) {
+		/* we need to disable interrupt to simulate ONESHOT mode,
+		 * do it before clearing the interrupt to avoid race */
+		if (dev->mode != CLOCK_EVT_MODE_PERIODIC)
+			gptimer_disable(t);
+
+		gptimer_clear_status(t);
+		dev->event_handler(dev);
+
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static struct irqaction comcerto_timer1_irq = {
+	.name           = "timer1",
+	.flags          = IRQF_DISABLED | IRQF_TIMER,
+	.handler        = comcerto_timer1_interrupt,
+};
+
+static void __init comcerto_clockevents_init(void)
+{
+	struct comcerto_gptimer *t = &timers[TID_CLOCKEVENT];
+
+	clockevent.mult = div_sc(COMCERTO_DEFAULTAHBCLK, NSEC_PER_SEC, clockevent.shift);
+	clockevent.max_delta_ns = clockevent_delta2ns(0x3fffffff, &clockevent);
+	clockevent.min_delta_ns = clockevent_delta2ns(1, &clockevent);
+	clockevent.cpumask = cpumask_of(0);
+	clockevents_register_device(&clockevent);
+
+	/* Clear all the timers except timer0  */
+	__raw_writel(COMCERTO_TIMER_CSP, COMCERTO_TIMER_STATUS);
+
+	/* Register interrupt handler for interrupt on IRQ_TIMERB*/
+	setup_irq(IRQ_TIMER1, &comcerto_timer1_irq);
+
+	/* Set and enable the system timer */
+	gptimer_set_bound(t, 0, COMCERTO_DEFAULTAHBCLK * 1000000 / HZ);
+}
+
+static void __init comcerto_timer_init(void)
+{
+	/*
+	 * DO NOT MODIFY THE CONFIGURATION OF TIMER0
+	 * It is used by the MSP
+	 * For C1000 FPP will be using TIMER2
+	 */
+
+	comcerto_clocksource_init();
+	comcerto_clockevents_init();
+}
+
+struct sys_timer comcerto_timer = {
+	.init           = comcerto_timer_init,
+};
-- 
1.5.4.3


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gistfile3.txt

[PATCH 3/3] Add irqs definition and handler for Mindspeed Comcerto platform
stanleymiao at gmail.com stanleymiao at gmail.com
Thu Oct 14 04:38:09 EDT 2010

    Previous message: [PATCH 2/3] Add hardware timer support for Mindspeed Comcerto platflorm
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From: Stanley.Miao <stanley.miao at windriver.com>

the Comcerto interrupt controller supports more than 32 peripheral interrupts,
so two interrupt status registers and associated mask registers are required.

Signed-off-by: Stanley.Miao <stanley.miao at windriver.com>
---
 arch/arm/mach-comcerto/Makefile                    |    2 +-
 arch/arm/mach-comcerto/board-c1kmfcn_evm.c         |    1 +
 arch/arm/mach-comcerto/comcerto-1000.c             |   41 ++++
 .../arm/mach-comcerto/include/mach/comcerto-1000.h |    1 +
 .../include/mach/comcerto-1000/intr.h              |   78 ++++++++
 .../include/mach/comcerto-1000/irqs.h              |  121 ++++++++++++
 arch/arm/mach-comcerto/include/mach/hardware.h     |    1 +
 arch/arm/mach-comcerto/include/mach/irq.h          |  155 +++++++++++++++
 arch/arm/mach-comcerto/include/mach/irqs.h         |   21 ++
 arch/arm/mach-comcerto/irq.c                       |  200 ++++++++++++++++++++
 10 files changed, 620 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-comcerto/include/mach/comcerto-1000/intr.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/comcerto-1000/irqs.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/irq.h
 create mode 100644 arch/arm/mach-comcerto/include/mach/irqs.h
 create mode 100644 arch/arm/mach-comcerto/irq.c

diff --git a/arch/arm/mach-comcerto/Makefile b/arch/arm/mach-comcerto/Makefile
index c514d20..b4c369d 100644
--- a/arch/arm/mach-comcerto/Makefile
+++ b/arch/arm/mach-comcerto/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y := time.o
+obj-y := irq.o time.o
 
 obj-$(CONFIG_ARCH_M83XXX)			+= comcerto-1000.o
 obj-$(CONFIG_EVM_C1KMFCN_EVM)			+= board-c1kmfcn_evm.o
diff --git a/arch/arm/mach-comcerto/board-c1kmfcn_evm.c b/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
index 74a7da3..3dd0b6f 100644
--- a/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
+++ b/arch/arm/mach-comcerto/board-c1kmfcn_evm.c
@@ -69,6 +69,7 @@ static void __init platform_map_io(void)
 
 static void __init platform_irq_init(void)
 {
+	device_irq_init();
 }
 
 static void __init platform_init(void)
diff --git a/arch/arm/mach-comcerto/comcerto-1000.c b/arch/arm/mach-comcerto/comcerto-1000.c
index 09032ea..2503871 100644
--- a/arch/arm/mach-comcerto/comcerto-1000.c
+++ b/arch/arm/mach-comcerto/comcerto-1000.c
@@ -28,6 +28,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
+#include <mach/irq.h>
+#include <mach/irqs.h>
 
 /***********************************************************
  *   Virtual address Mapping                               *
@@ -144,3 +146,42 @@ void __init device_map_io(void)
 	iotable_init(comcerto_io_desc, ARRAY_SIZE(comcerto_io_desc));
 }
 
+/* IRQ configuration table */
+static struct comcerto_irq_desc comcerto_irq_table[] __initdata = {
+	{IRQ_EMAC0_BATCH,		handle_level_irq,			1},
+	{IRQ_EMAC1_BATCH,		handle_level_irq,			2},
+	{IRQ_ARAM,			comcerto_handle_secondary_level_irq,	3},
+	{IRQ_PCIe0_EXT,			handle_level_irq,			4},
+	{IRQ_PCIe1_EXT,			handle_level_irq,			5},
+	{IRQ_PCIe0_INT,			comcerto_handle_secondary_level_irq,	6},
+	{IRQ_PCIe1_INT,			comcerto_handle_secondary_level_irq,	7},
+	{IRQ_USB0,			comcerto_handle_secondary_level_irq,	8},
+	{STATUS_REG_1,			NULL,					9},
+	{IRQ_PTP0,			handle_level_irq,			10},
+	{IRQ_TIMER1,			comcerto_handle_secondary_level_irq,	11},
+	{IRQ_TIMER3,			comcerto_handle_secondary_level_irq,	12},
+	{IRQ_TIMER4,			comcerto_handle_secondary_level_irq,	13},
+	{IRQ_TIMER5,			comcerto_handle_secondary_level_irq,	14},
+	{IRQ_SPI,			comcerto_handle_secondary_level_irq,	15},
+	{IRQ_EMAC0,			comcerto_handle_secondary_level_irq,	16},
+	{IRQ_EMAC1,			comcerto_handle_secondary_level_irq,	17},
+	{IRQ_IPSEC_WRAP,		handle_level_irq,			18},
+	{IRQ_I2C,			comcerto_handle_secondary_level_irq,	19},
+	{IRQ_CSP_PMU,			handle_level_irq,			-1},
+	{IRQ_UART1,			comcerto_handle_secondary_level_irq,	-1},
+	{IRQ_UART0,			comcerto_handle_secondary_level_irq,	-1},
+	{IRQ_G2,			handle_level_irq,			-1},
+	{IRQ_G1,			handle_level_irq,			-1},
+	{IRQ_G0,			handle_level_irq,			-1},
+	{IRQ_FPP,			handle_level_irq,			-1},
+	{IRQ_CSPVED1RX,			handle_level_irq,			-1},
+	{IRQ_CSPVED0RX,			handle_level_irq,			-1},
+	{IRQ_SPDRV_ACP_REQ,		handle_level_irq,			-1},
+	{IRQ_SPDRV_ACP_WORK_DONE,	handle_level_irq,			-1}
+};
+
+void __init device_irq_init(void)
+{
+	comcerto_irq_init(comcerto_irq_table, ARRAY_SIZE(comcerto_irq_table));
+}
+
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
index 10086c4..ac9cd21 100644
--- a/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000.h
@@ -90,5 +90,6 @@
 #define APB_VADDR(x)            ((x) - COMCERTO_AHB_APB_BASE + APB_VADDR_BASE)
 
 #include <mach/comcerto-1000/timer.h>
+#include <mach/comcerto-1000/intr.h>
 
 #endif
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000/intr.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000/intr.h
new file mode 100644
index 0000000..61c2e3a
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000/intr.h
@@ -0,0 +1,78 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/comcerto-1000/intr.h
+ *
+ *  Copyright (C) 2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTINTCULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __INTR__H__
+#define __INTR__H__
+
+/*  Comcerto Interrupt Controller */
+#define COMCERTO_INTC_STATUS_REG_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x00))
+#define COMCERTO_INTC_CLEAR_STATUS_REG_0		APB_VADDR((COMCERTO_APB_INTC_BASE + 0x00))
+#define COMCERTO_INTC_SET_STATUS_REG_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x04))
+#define COMCERTO_INTC_ARM0_IRQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x08))
+#define COMCERTO_INTC_ARM0_FIQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x0C))
+#define COMCERTO_INTC_ARM1_IRQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x10))
+#define COMCERTO_INTC_ARM1_FIQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x14))
+#define COMCERTO_INTC_ARM1_CONTROL_REG			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x18))
+#define COMCERTO_INTC_IRQ_ACK_TEST_REG			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x1C))
+#define COMCERTO_INTC_STATUS_REG_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x20))
+#define COMCERTO_INTC_CLEAR_STATUS_REG_1		APB_VADDR((COMCERTO_APB_INTC_BASE + 0x20))
+#define COMCERTO_INTC_SET_STATUS_REG_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x24))
+#define COMCERTO_INTC_ARM0_IRQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x28))
+#define COMCERTO_INTC_ARM0_FIQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x2C))
+#define COMCERTO_INTC_ARM1_IRQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x30))
+#define COMCERTO_INTC_ARM1_FIQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x34))
+#define COMCERTO_INTC_STATUS_MASK_REG_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x38))
+#define COMCERTO_INTC_ARM0_PRTY_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x40))
+#define COMCERTO_INTC_ARM0_PRTY_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x44))
+#define COMCERTO_INTC_ARM0_PRTY_2			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x48))
+#define COMCERTO_INTC_ARM0_PRTY_3			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x4C))
+#define COMCERTO_INTC_ARM0_PRTY_4			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x50))
+#define COMCERTO_INTC_ARM0_PRTY_5			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x54))
+#define COMCERTO_INTC_ARM0_PRTY_6			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x58))
+#define COMCERTO_INTC_ARM0_PRTY_7			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x5C))
+#define COMCERTO_INTC_ARM0_IRQ_WNR			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x60))
+#define COMCERTO_INTC_ARM0_SELFCLEAR			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x64))
+#define COMCERTO_INTC_FIQ_PRTY_EN			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x68))
+#define COMCERTO_INTC_TDMA_STS				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x70))
+#define COMCERTO_INTC_TDMA_CTRL				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x74))
+#define COMCERTO_INTC_TDMA_SET				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x78))
+#define COMCERTO_INTC_ARM1_PRTY_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x80))
+#define COMCERTO_INTC_ARM1_PRTY_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x84))
+#define COMCERTO_INTC_ARM1_PRTY_2			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x88))
+#define COMCERTO_INTC_ARM1_PRTY_3			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x8C))
+#define COMCERTO_INTC_ARM1_PRTY_4			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x90))
+#define COMCERTO_INTC_ARM1_PRTY_5			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x94))
+#define COMCERTO_INTC_ARM1_PRTY_6			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x98))
+#define COMCERTO_INTC_ARM1_PRTY_7			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x9C))
+#define COMCERTO_INTC_ARM1_IRQ_WNR			APB_VADDR((COMCERTO_APB_INTC_BASE + 0xA0))
+#define COMCERTO_INTC_ARM0_IRQ_WNR_VBA			APB_VADDR((COMCERTO_APB_INTC_BASE + 0xB0))
+#define COMCERTO_INTC_ARM1_IRQ_WNR_VBA			APB_VADDR((COMCERTO_APB_INTC_BASE + 0xB4))
+#define COMCERTO_INTC_ARM0_STS_VEC_ADDR(nb)		APB_VADDR((COMCERTO_APB_INTC_BASE + 0x100 + 4nb))
+#define COMCERTO_INTC_ARM1_STS_VEC_ADDR(nb)		APB_VADDR((COMCERTO_APB_INTC_BASE + 0x180 + 4nb))
+
+#define COMCERTO_INTC_CSP_IRQMASK_0     COMCERTO_INTC_ARM0_IRQMASK_0
+#define COMCERTO_INTC_CSP_IRQMASK_1     COMCERTO_INTC_ARM0_IRQMASK_1
+#define COMCERTO_INTC_CSP_FIQMASK_0     COMCERTO_INTC_ARM0_FIQMASK_0
+#define COMCERTO_INTC_CSP_FIQMASK_1     COMCERTO_INTC_ARM0_FIQMASK_1
+
+#define COMCERTO_INTC_CSP_IRQ_WNR       COMCERTO_INTC_ARM0_IRQ_WNR
+#define COMCERTO_INTC_CSP_PRTY_0        COMCERTO_INTC_ARM0_PRTY_0
+
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-1000/irqs.h b/arch/arm/mach-comcerto/include/mach/comcerto-1000/irqs.h
new file mode 100644
index 0000000..7f59a77
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-1000/irqs.h
@@ -0,0 +1,121 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/comcerto-1000/irqs.h
+ *
+ *  Copyright (C) 2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __COMCERTO_IRQS_H__
+#define __COMCERTO_IRQS_H__
+
+/* INTC0 32 First IRQs*/
+#define IRQ_TIMER0			31
+#define IRQ_TIMER1			30
+#define IRQ_TIMER2			29
+#define IRQ_TIMER3			28
+#define IRQ_TIMER4			27
+#define IRQ_TIMER5			26
+/*	#define IRQ_Reserved		25*/
+#define IRQ_EMAC1_BATCH			24
+#define IRQ_EMAC0_BATCH			23
+#define IRQ_ARAM			22
+#define IRQ_I2C				21
+#define IRQ_THERMAL			20
+#define IRQ_HWFAULT			19
+#define IRQ_DDRC			18
+#define IRQ_PCIe1_INT			17
+#define IRQ_PCIe1_EXT			16
+#define IRQ_PCIe0_INT			15
+#define IRQ_PCIe0_EXT			14
+#define IRQ_MDMA1			13
+#define IRQ_MDMA0			12
+#define IRQ_SPI				11
+#define IRQ_IPSEC_CORE			10
+#define IRQ_IPSEC_WRAP			9
+#define IRQ_TDMA			8
+#define IRQ_EMAC1			7
+#define IRQ_EMAC0			6
+#define IRQ_USB0			5
+#define IRQ_TDM_TIMER			4
+#define IRQ_PTP2			3
+#define IRQ_PTP1			2
+#define IRQ_PTP0			1
+#define STATUS_REG_1			0
+
+/* INTC1 32 next IRQs*/
+/*	#define IRQ_Reserved		31*/
+/*	#define IRQ_Reserved		30*/
+/*	#define IRQ_Reserved		29*/
+#define IRQ_TDMA_TxAHBErr		(28 + 32)
+#define IRQ_TDMA_RxAHBErr		(27 + 32)
+#define IRQ_UART1			(26 + 32)
+#define IRQ_CSP_HIDRV			(25 + 32)
+#define IRQ_CSPVED1TX			(24 + 32)
+#define IRQ_CSPVED1RX			(23 + 32)
+#define IRQ_CSPVED0TX			(22 + 32)
+#define IRQ_CSPVED0RX			(21 + 32)
+#define IRQ_TOHOST			(20 + 32)
+#define IRQ_FROMHOST			(19 + 32)
+#define IRQ_MSP_PMU			(18 + 32)
+#define IRQ_CSP_PMU			(17 + 32)
+/*	#define IRQ_Reserved		16*/
+/*	#define IRQ_Reserved		15*/
+/*	#define IRQ_Reserved		14*/
+#define IRQ_SPDRV_ACP_REQ		(13 + 32)
+#define IRQ_SPDRV_ACP_WORK_DONE		(12 + 32)
+#define IRQ_VED				(11 + 32)
+#define IRQ_TDMA_IND			(10 + 32)
+#define IRQ_UART0			(9 + 32)
+#define IRQ_G7				(8 + 32)
+#define IRQ_G6				(7 + 32)
+#define IRQ_G5				(6 + 32)
+#define IRQ_G4				(5 + 32)
+#define IRQ_G3				(4 + 32)
+#define IRQ_G2				(3 + 32)
+#define IRQ_G1				(2 + 32)
+#define IRQ_G0				(1 + 32)
+#define STATUS_REG_0			(0 + 32)
+
+/* Software decoded interrupts used by PCIE */
+#define IRQ_PCIE0_MSI0			64
+#define IRQ_PCIE0_MSI1			65
+#define IRQ_PCIE0_MSI2			66
+#define IRQ_PCIE0_MSI3			67
+
+#define IRQ_PCIE0_INTA			68
+#define IRQ_PCIE0_INTB			69
+#define IRQ_PCIE0_INTC			70
+#define IRQ_PCIE0_INTD			71
+
+#define IRQ_PCIE1_MSI0			72
+#define IRQ_PCIE1_MSI1			73
+#define IRQ_PCIE1_MSI2			74
+#define IRQ_PCIE1_MSI3			75
+
+#define IRQ_PCIE1_INTA			76
+#define IRQ_PCIE1_INTB			77
+#define IRQ_PCIE1_INTC			78
+#define IRQ_PCIE1_INTD			79
+
+
+#define NR_IRQS				80
+
+#define IRQ_TIMERB		IRQ_TIMER1
+#define IRQ_FPP			IRQ_CSP_HIDRV
+
+#define FPP_IRQ_FROMHOST	IRQ_FROMHOST
+#define FPP_IRQ_TOHOST		IRQ_TOHOST
+#define FPP_IRQ_EVENT		IRQ_FPP
+#endif
diff --git a/arch/arm/mach-comcerto/include/mach/hardware.h b/arch/arm/mach-comcerto/include/mach/hardware.h
index 577289d..da023b2 100644
--- a/arch/arm/mach-comcerto/include/mach/hardware.h
+++ b/arch/arm/mach-comcerto/include/mach/hardware.h
@@ -32,6 +32,7 @@
 struct sys_timer;
 extern struct sys_timer comcerto_timer;
 extern void device_map_io(void);
+extern void device_irq_init(void);
 #endif
 
 #endif
diff --git a/arch/arm/mach-comcerto/include/mach/irq.h b/arch/arm/mach-comcerto/include/mach/irq.h
new file mode 100644
index 0000000..b5b8a54
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/irq.h
@@ -0,0 +1,155 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/irq.h
+ *
+ *  Copyright (C) 2004,2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IRQ_H
+#define __ASM_ARCH_IRQ_H
+
+#include <linux/irq.h>
+#include <asm/io.h>
+
+extern spinlock_t comcerto_irq_lock;
+extern int noirqdebug;
+
+struct comcerto_irq_desc {
+	char num;
+	irq_flow_handler_t handler;
+	unsigned int prio;
+};
+
+void comcerto_handle_secondary_level_irq(unsigned int irq, struct irq_desc *);
+void __init comcerto_irq_init(struct comcerto_irq_desc *irq_table, int size);
+
+/* For all devices with priority support we provide a call to change STATUS1
+ * priority from the EVM-specific code. Priority value should be in [0..31]
+ * range.
+ */
+void __init comcerto_irq_status1_priority_set(unsigned char priority);
+
+static inline u32 comcerto_irq_to_mask(unsigned int irq)
+{
+	return 1 << ((irq) & 0x1f);
+}
+
+static inline void comcerto_irq_mask_0(unsigned int irq)
+{
+	unsigned long flags;
+	unsigned long mask;
+
+	spin_lock_irqsave(&comcerto_irq_lock, flags);
+	mask = __raw_readl(COMCERTO_INTC_CSP_IRQMASK_0);
+	mask &= ~comcerto_irq_to_mask(irq);
+	__raw_writel(mask, COMCERTO_INTC_CSP_IRQMASK_0);
+	spin_unlock_irqrestore(&comcerto_irq_lock, flags);
+}
+
+static inline void comcerto_irq_mask_1(unsigned int irq)
+{
+	unsigned long flags;
+	unsigned long mask;
+
+	spin_lock_irqsave(&comcerto_irq_lock, flags);
+	mask = __raw_readl(COMCERTO_INTC_CSP_IRQMASK_1);
+	mask &= ~comcerto_irq_to_mask(irq);
+	__raw_writel(mask, COMCERTO_INTC_CSP_IRQMASK_1);
+	spin_unlock_irqrestore(&comcerto_irq_lock, flags);
+}
+
+static inline void comcerto_irq_mask(unsigned int irq)
+{
+	if (irq < 32)
+		comcerto_irq_mask_0(irq);
+	else
+		comcerto_irq_mask_1(irq);
+}
+
+static inline void comcerto_irq_ack_0(unsigned int irq)
+{
+	__raw_writel(comcerto_irq_to_mask(irq), COMCERTO_INTC_STATUS_REG_0);
+}
+
+static inline void comcerto_irq_ack_1(unsigned int irq)
+{
+	__raw_writel(comcerto_irq_to_mask(irq), COMCERTO_INTC_STATUS_REG_1);
+}
+
+static inline void comcerto_irq_ack(unsigned int irq)
+{
+	if (irq < 32)
+		comcerto_irq_ack_0(irq);
+	else
+		comcerto_irq_ack_1(irq);
+}
+
+static inline void comcerto_irq_unmask_0(unsigned int irq)
+{
+	unsigned long flags;
+	unsigned long mask;
+
+	spin_lock_irqsave(&comcerto_irq_lock, flags);
+	mask = __raw_readl(COMCERTO_INTC_CSP_IRQMASK_0);
+	mask |= comcerto_irq_to_mask(irq);
+	__raw_writel(mask, COMCERTO_INTC_CSP_IRQMASK_0);
+	spin_unlock_irqrestore(&comcerto_irq_lock, flags);
+}
+
+static inline void comcerto_irq_unmask_1(unsigned int irq)
+{
+	unsigned long flags;
+	unsigned long mask;
+
+	spin_lock_irqsave(&comcerto_irq_lock, flags);
+	mask = __raw_readl(COMCERTO_INTC_CSP_IRQMASK_1);
+	mask |= comcerto_irq_to_mask(irq);
+	__raw_writel(mask, COMCERTO_INTC_CSP_IRQMASK_1);
+	spin_unlock_irqrestore(&comcerto_irq_lock, flags);
+}
+
+static inline void comcerto_irq_unmask(unsigned int irq)
+{
+	if (irq < 32)
+		comcerto_irq_unmask_0(irq);
+	else
+		comcerto_irq_unmask_1(irq);
+}
+
+static inline void comcerto_softirq_set(unsigned int irq)
+{
+	void *reg;
+
+	if (irq < 32)
+		reg = (void *)COMCERTO_INTC_SET_STATUS_REG_0;
+	else
+		reg = (void *)COMCERTO_INTC_SET_STATUS_REG_1;
+
+	__raw_writel(comcerto_irq_to_mask(irq), reg);
+}
+
+static inline int comcerto_softirq_check(unsigned int irq)
+{
+	void *reg;
+
+	if (irq < 32)
+		reg = (void *)COMCERTO_INTC_STATUS_REG_0;
+	else
+		reg = (void *)COMCERTO_INTC_STATUS_REG_1;
+
+	return __raw_readl(reg) & comcerto_irq_to_mask(irq) ? 1 : 0;
+}
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-comcerto/include/mach/irqs.h b/arch/arm/mach-comcerto/include/mach/irqs.h
new file mode 100644
index 0000000..409281b
--- /dev/null
+++ b/arch/arm/mach-comcerto/include/mach/irqs.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/irqs.h
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#if defined(CONFIG_ARCH_M83XXX)
+	#include <mach/comcerto-1000/irqs.h>
+#else
+	#error "Unsupported CPU"
+#endif
+
+#endif  /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-comcerto/irq.c b/arch/arm/mach-comcerto/irq.c
new file mode 100644
index 0000000..4288ba1
--- /dev/null
+++ b/arch/arm/mach-comcerto/irq.c
@@ -0,0 +1,200 @@
+/*
+ *  linux/arch/arm/mach-comcerto/irq.c
+ *
+ *  Copyright (C) 2004-2008 Mindspeed Technologies, Inc.
+ *  Copyright (c) 2010 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/ptrace.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+
+#include <asm/irq.h>
+#include <linux/io.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+
+#include <mach/irq.h>
+#include <mach/irqs.h>
+
+spinlock_t comcerto_irq_lock;
+
+static void comcerto_irq_mask_ack_0(unsigned int irq)
+{
+	comcerto_irq_mask_0(irq);
+	comcerto_irq_ack_0(irq);
+}
+
+static void comcerto_irq_mask_ack_1(unsigned int irq)
+{
+	comcerto_irq_mask_1(irq);
+	comcerto_irq_ack_1(irq);
+}
+
+static int comcerto_set_irq_type_0(unsigned int irq, unsigned int type)
+{
+	return 0;
+}
+
+static int comcerto_set_irq_type_1(unsigned int irq, unsigned int type)
+{
+	return 0;
+}
+
+static struct irq_chip comcerto_irq_chip_0 = {
+	.name		= "Comcerto INTC0",
+	.disable	= comcerto_irq_mask_0,
+	.ack		= comcerto_irq_ack_0,
+	.mask		= comcerto_irq_mask_0,
+	.unmask		= comcerto_irq_unmask_0,
+	.set_type	= comcerto_set_irq_type_0,
+	.mask_ack	= comcerto_irq_mask_ack_0,
+};
+
+static struct irq_chip comcerto_irq_chip_1 = {
+	.name		= "Comcerto INTC1",
+	.disable	= comcerto_irq_mask_1,
+	.ack		= comcerto_irq_ack_1,
+	.mask		= comcerto_irq_mask_1,
+	.unmask		= comcerto_irq_unmask_1,
+	.set_type	= comcerto_set_irq_type_1,
+	.mask_ack	= comcerto_irq_mask_ack_1,
+};
+
+void comcerto_handle_secondary_level_irq(unsigned int irq,
+						struct irq_desc *desc)
+{
+	struct irqaction *action;
+	irqreturn_t action_ret;
+
+	raw_spin_lock(&desc->lock);
+	desc->chip->mask(irq);
+
+	if (unlikely(desc->status & IRQ_INPROGRESS))
+		goto out_unlock;
+	desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+	kstat_incr_irqs_this_cpu(irq, desc);
+	/*
+	 * If its disabled or no action available
+	 * keep it masked and get out of here
+	 */
+	action = desc->action;
+	if (unlikely(!action || (desc->status & IRQ_DISABLED))) {
+		desc->status |= IRQ_PENDING;
+		goto out_unlock;
+	}
+
+	desc->status |= IRQ_INPROGRESS;
+	desc->status &= ~IRQ_PENDING;
+	raw_spin_unlock(&desc->lock);
+
+	action_ret = handle_IRQ_event(irq, action);
+	if (!noirqdebug)
+		note_interrupt(irq, desc, action_ret);
+
+	raw_spin_lock(&desc->lock);
+	desc->status &= ~IRQ_INPROGRESS;
+
+	desc->chip->ack(irq);
+
+	if (unlikely(desc->status & IRQ_ONESHOT))
+		desc->status |= IRQ_MASKED;
+	else if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
+		desc->chip->unmask(irq);
+out_unlock:
+	raw_spin_unlock(&desc->lock);
+}
+
+static u8 comcerto_status0_priorities[32] __initdata = {0, };
+
+static __init void comcerto_irq_priority_set(unsigned int irq, unsigned int prio)
+{
+	unsigned int prio_reg, prio_shift, prio_mask, tmp;
+
+	/* we store +1 priority to reserve zero for non-used slots */
+	comcerto_status0_priorities[irq] = prio + 1;
+	prio_reg = COMCERTO_INTC_CSP_PRTY_0 + 4 * (prio / 4);
+	prio_shift = ((prio % 4) << 3);
+	prio_mask = 0x1f << prio_shift;
+	tmp = __raw_readl(prio_reg) & ~prio_mask;
+	tmp |= irq << prio_shift;
+	__raw_writel(tmp, prio_reg);
+}
+
+void __init comcerto_irq_status1_priority_set(unsigned char priority)
+{
+	int i;
+	unsigned long flags;
+
+	if ((priority & ~31) != 0)
+		BUG();
+
+	priority++;	/*  */
+
+	spin_lock_irqsave(&comcerto_irq_lock, flags);
+
+	/* look at all interrupts except STATUS1 and
+	 * fix all priorities >= specified */
+	for (i = 1; i < 32; i++)
+		if (comcerto_status0_priorities[i] >= priority \
+				&& comcerto_status0_priorities[i] > 0)
+			comcerto_status0_priorities[i]++;
+
+	comcerto_status0_priorities[0] = priority;
+
+	/* program all non-zero priorities,
+	 * don't forget to decrement priority value taken from array */
+	for (i = 0; i < 32; i++)
+		if (comcerto_status0_priorities[i] > 0)
+			comcerto_irq_priority_set(i, comcerto_status0_priorities[i] - 1);
+
+	spin_unlock_irqrestore(&comcerto_irq_lock, flags);
+}
+
+void __init comcerto_irq_init(struct comcerto_irq_desc *irq_table, int size)
+{
+	unsigned int irq;
+	int i;
+
+	spin_lock_init(&comcerto_irq_lock);
+
+	/* mask all interrupts */
+	__raw_writel(0, COMCERTO_INTC_CSP_IRQMASK_0);
+	__raw_writel(0, COMCERTO_INTC_CSP_IRQMASK_1);
+
+	for (i = 0; i < size; i++) {
+		irq = irq_table[i].num;
+
+		/* setup interrupt handler and priority */
+		if (irq < 32) {
+			/* All STATUS0 interrupts must be setup from
+			 * the single table declared in comcerto-xxx.c
+			 * file. Use description index as a priority.
+			 */
+			comcerto_irq_priority_set(irq, irq_table[i].prio);
+			set_irq_chip(irq, &comcerto_irq_chip_0);
+		} else
+			set_irq_chip(irq, &comcerto_irq_chip_1);
+
+		if (irq_table[i].handler != NULL) {
+			set_irq_handler(irq, irq_table[i].handler);
+			set_irq_flags(irq, IRQF_VALID);
+		}
+	}
+}
-- 
1.5.4.3


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