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hiroki@amd64:~ % pciconf -l -v | |
hostb0@pci0:0:0:0: class=0x060000 card=0x80a31043 chip=0x31881106 rev=0x01 | |
hdr=0x00 | |
vendor = 'VIA Technologies, Inc.' | |
device = 'VT8385 [K8T800 AGP] Host Bridge' | |
class = bridge | |
subclass = HOST-PCI | |
pcib1@pci0:0:1:0: class=0x060400 card=0x00000000 chip=0xb1881106 rev=0x00 | |
hdr=0x01 | |
vendor = 'VIA Technologies, Inc.' |
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STR9100>go 0x1000000 | |
## Starting application at 0x01000000 ... | |
KDB: debugger backends: ddb | |
KDB: current backend: ddb | |
Copyright (c) 1992-2012 The FreeBSD Project. | |
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 | |
The Regents of the University of California. All rights reserved. | |
FreeBSD is a registered trademark of The FreeBSD Foundation. | |
FreeBSD 9.1-RELEASE #0: Mon Aug 8 05:55:07 UTC 2016 | |
root@jail9:/root/obj91/arm.arm/root/freebsd-release-9.1.0/sys/CNS11XXNAS arm |
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Starting kernel ... | |
KDB: debugger backends: ddb | |
KDB: current backend: ddb | |
Copyright (c) 1992-2014 The FreeBSD Project. | |
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 | |
The Regents of the University of California. All rights reserved. | |
FreeBSD is a registered trademark of The FreeBSD Foundation. | |
FreeBSD 10.0-RELEASE #8 12f6d44(rel10_modify)-dirty: Fri Aug 12 11:24:49 JST 201 | |
6 |
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Marvell>> tftpboot 400100 Buffalo_WZR-AMPG300NH_kernel.kbin | |
Using egiga0 device | |
TFTP from server 10.10.10.3; our IP address is 10.10.10.108 | |
Filename 'Buffalo_WZR-AMPG300NH_kernel.kbin'. | |
Load address: 0x400100 | |
Loading: ################################################################# | |
################################################################# | |
################################################################# | |
################################################################# | |
################################################################# |
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execute ssb base elf kernel | |
CFE> ifconfig eth0 -addr=10.10.10.200 | |
CFE> boot -elf 10.10.10.3:Buffalo_WHR-HP-G54_kernel | |
write ssb base image to flash | |
CFE> ifconfig eth0 -addr=10.10.10.200 | |
CFE> flash -noheader 10.10.10.3:Buffalo_WHR-G54S.trx flash1.trx | |
CFE> boot -raw -z -addr=0x80001000 -max=0x3a0000 flash0.os: |
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Starting program at 0x80001000 | |
entry: mips_init() | |
Cache info: | |
picache_stride = 4096 | |
picache_loopcount = 2 | |
pdcache_stride = 2048 | |
pdcache_loopcount = 2 | |
max line size = 16 | |
cpu0: Broadcom processor v7.144 | |
MMU: Standard TLB, 32 entries (1K 4K 16K 64K 256K 1M 16M 64M 256M pg sizes) |
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Sep 18 18:04:56 10.0.1.18 kernel: maxproc limit exceeded by uid 0 (pid 93); see | |
tuning(7) and login.conf(5) | |
Sep 18 18:05:23 10.0.1.18 kernel: maxproc limit exceeded by uid 0 (pid 218); see | |
tuning(7) and login.conf(5) | |
Sep 18 18:04:34 10.0.1.18 cron[28814]: (root) CMD (/tmp/smlogger.sh) | |
Sep 18 18:04:34 10.0.1.18 cron[28813]: (root) CMD (rm /tmp/smaddr) | |
Sep 18 18:05:09 10.0.1.18 cron[218]: (CRON) error (can't fork) | |
Sep 18 18:05:01 10.0.1.18 inetd[93]: fork: Resource temporarily unavailable | |
Sep 18 18:10:28 10.0.1.18 kernel: maxproc limit exceeded by uid 0 (pid 218); see | |
tuning(7) and login.conf(5) |
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BUFFALO U-BOOT Ver 1.00 | |
== CPU:680MHz, DDR:340MHz, AHB:170MHz == | |
AP96 (ar7100) U-boot 0.0.1 | |
DRAM: 128 MB | |
Top of RAM usable for U-Boot at: 84000000 | |
Reserving 265k for U-Boot at: 83fbc000 | |
Reserving 192k for malloc() at: 83f8c000 |
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Starting kernel ... | |
entry: mips_init() | |
Cache info: | |
picache_stride = 4096 | |
picache_loopcount = 2 | |
pdcache_stride = 4096 | |
pdcache_loopcount = 2 | |
cpu0: MIPS Technologies processor v11.128 | |
MMU: Standard TLB, 16 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes) |
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microserver % sudo ./mspdebug load-bsl | |
Password: | |
MSPDebug version 0.24 - debugging tool for MSP430 MCUs | |
Copyright (C) 2009-2016 Daniel Beer <dlbeer@gmail.com> | |
This is free software; see the source for copying conditions. There is NO | |
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
Chip info database from MSP430.dll v3.3.1.4 Copyright (C) 2013 TI, Inc. | |
Opening interface 0 (config 0)... | |
Found endpoints: IN: 0x81, OUT: 0x01 |