kaze rules

gouraud-diff.diff

diff --git a/rtl/src/color_thrust.rs b/rtl/src/color_thrust.rs
index 58b94d5..5fa8482 100644
--- a/rtl/src/color_thrust.rs
+++ b/rtl/src/color_thrust.rs
@@ -19,15 +19,25 @@ pub const REG_W1_DY_ADDR: u32 = 6;
 pub const REG_W2_MIN_ADDR: u32 = 7;
 pub const REG_W2_DX_ADDR: u32 = 8;
 pub const REG_W2_DY_ADDR: u32 = 9;
-
-pub const REG_COLOR_ADDR: u32 = 10;
+pub const REG_R_MIN_ADDR: u32 = 10;
+pub const REG_R_DX_ADDR: u32 = 11;
+pub const REG_R_DY_ADDR: u32 = 12;
+pub const REG_G_MIN_ADDR: u32 = 13;
+pub const REG_G_DX_ADDR: u32 = 14;
+pub const REG_G_DY_ADDR: u32 = 15;
+pub const REG_B_MIN_ADDR: u32 = 16;
+pub const REG_B_DX_ADDR: u32 = 17;
+pub const REG_B_DY_ADDR: u32 = 18;
+pub const REG_A_MIN_ADDR: u32 = 19;
+pub const REG_A_DX_ADDR: u32 = 20;
+pub const REG_A_DY_ADDR: u32 = 21;

 pub fn generate<'a>(c: &'a Context<'a>) -> &Module<'a> {
     let m = c.module("ColorThrust");

     m.output("reg_bus_ready", m.high());
     let reg_bus_enable = m.input("reg_bus_enable", 1);
-    let reg_bus_addr_bit_width = 4;
+    let reg_bus_addr_bit_width = 5;
     let reg_bus_addr = m.input("reg_bus_addr", reg_bus_addr_bit_width);
     let reg_bus_write = m.input("reg_bus_write", 1);
     let reg_bus_write_data = m.input("reg_bus_write_data", 32);
@@ -124,12 +134,10 @@ pub fn generate<'a>(c: &'a Context<'a>) -> &Module<'a> {
     let w1 = interpolant("w1", 32, REG_W1_MIN_ADDR, REG_W1_DX_ADDR, REG_W1_DY_ADDR);
     let w2 = interpolant("w2", 32, REG_W2_MIN_ADDR, REG_W2_DX_ADDR, REG_W2_DY_ADDR);

-    let color = m.reg("color", 32);
-    color.drive_next(if_(reg_bus_write_enable & reg_bus_addr.eq(m.lit(REG_COLOR_ADDR, reg_bus_addr_bit_width)), {
-        reg_bus_write_data
-    }).else_({
-        color.value
-    }));
+    let r = interpolant("r", 24, REG_R_MIN_ADDR, REG_R_DX_ADDR, REG_R_DY_ADDR).bits(19, 12);
+    let g = interpolant("g", 24, REG_G_MIN_ADDR, REG_G_DX_ADDR, REG_G_DY_ADDR).bits(19, 12);
+    let b = interpolant("b", 24, REG_B_MIN_ADDR, REG_B_DX_ADDR, REG_B_DY_ADDR).bits(19, 12);
+    let a = interpolant("a", 24, REG_A_MIN_ADDR, REG_A_DX_ADDR, REG_A_DY_ADDR).bits(19, 12);

     m.output("color_buffer_bus_ready", m.high());
     let color_buffer_bus_enable = m.input("color_buffer_bus_enable", 1);
@@ -148,7 +156,7 @@ pub fn generate<'a>(c: &'a Context<'a>) -> &Module<'a> {
         if_(color_buffer_bus_write_enable, {
             color_buffer_bus_write_data
         }).else_({
-            color.value
+            a.concat(r).concat(g).concat(b)
         }),
         color_buffer_bus_write_enable | (busy.value & !(w0.bit(31) | w1.bit(31) | w2.bit(31))));

diff --git a/rtl/src/xenowing.rs b/rtl/src/xenowing.rs
index 05538f4..b33b290 100644
--- a/rtl/src/xenowing.rs
+++ b/rtl/src/xenowing.rs
@@ -143,7 +143,7 @@ pub fn generate<'a>(c: &'a Context<'a>) -> &Module<'a> {
     let color_thrust = m.instance("color_thrust", "ColorThrust");

     color_thrust.drive_input("reg_bus_enable", interconnect.output("color_thrust_reg_bus_enable"));
-    color_thrust.drive_input("reg_bus_addr", interconnect.output("color_thrust_reg_bus_addr").bits(3, 0));
+    color_thrust.drive_input("reg_bus_addr", interconnect.output("color_thrust_reg_bus_addr").bits(4, 0));
     color_thrust.drive_input("reg_bus_write", interconnect.output("color_thrust_reg_bus_write"));
     color_thrust.drive_input("reg_bus_write_data", interconnect.output("color_thrust_reg_bus_write_data").bits(31, 0));
     //color_thrust.drive_input("reg_bus_write_byte_enable", interconnect.output("color_thrust_reg_bus_write_byte_enable"));