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yupferris/execute.sv

Created January 31, 2020 20:45
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execute.sv
module execute(
input wire logic reset_n,
input wire logic clk,
input wire logic [31:0] instruction,
input wire logic [31:0] register_file_read_data1,
input wire logic [31:0] register_file_read_data2,
input wire logic [31:0] alu_res,
input wire logic [31:0] pc,
input wire logic [63:0] cycle_counter_value,
input wire logic [63:0] instructions_retired_counter_value,
output wire logic [31:0] alu_lhs,
output wire logic [31:0] bus_addr,
output wire logic [3:0] bus_byte_enable,
output wire logic bus_read_req,
output wire logic [2:0] alu_op,
output wire logic alu_op_mod,
output wire logic [31:0] alu_rhs,
output wire logic [31:0] bus_write_data,
output wire logic bus_write_req,
output wire logic [31:0] next_pc,
output wire logic rd_value_write_enable,
output wire logic [31:0] rd_value_write_data
);
logic [31:0] node0;
logic [31:0] node1;
logic [31:0] node2;
logic [31:0] node3;
logic [31:0] node4;
logic [2:0] node5;
logic [31:0] node6;
logic [2:0] node7;
logic [31:0] node8;
logic [31:0] node9;
logic [31:0] node10;
logic [31:0] node11;
logic [31:0] node12;
logic [31:0] node13;
logic [4:0] node14;
logic [31:0] node15;
logic [31:0] node16;
logic [31:0] node17;
logic [31:0] node18;
logic [31:0] node19;
logic [31:0] node20;
logic [31:0] node21;
logic [31:0] node22;
logic [31:0] node23;
logic [31:0] node24;
logic [31:0] node25;
logic [31:0] node26;
logic [31:0] node27;
logic [31:0] node28;
logic [31:0] node29;
logic [31:0] node30;
logic [31:0] node31;
logic [31:0] node32;
logic [31:0] node33;
logic [2:0] node34;
logic [31:0] node35;
logic [31:0] node36;
logic [31:0] node37;
logic [31:0] node38;
logic [2:0] node39;
logic [31:0] node40;
logic [31:0] node41;
logic [31:0] node42;
logic [31:0] node43;
logic [31:0] node44;
logic [32:0] node45;
logic [31:0] node46;
logic [31:0] node47;
logic [31:0] node48;
logic [31:0] node49;
logic [31:0] node50;
logic [32:0] node51;
logic [32:0] node52;
logic [31:0] node53;
logic [31:0] node54;
logic [2:0] node55;
logic [31:0] node56;
logic [2:0] node57;
logic [31:0] node58;
logic [2:0] node59;
logic [31:0] node60;
logic [2:0] node61;
logic [31:0] node62;
logic [31:0] node63;
logic [31:0] node64;
logic [31:0] node65;
logic [63:0] node66;
logic [63:0] node67;
logic [31:0] node68;
logic [11:0] node69;
logic [63:0] node70;
logic [63:0] node71;
logic [31:0] node72;
logic [11:0] node73;
logic [31:0] node74;
logic [32:0] node75;
logic [31:0] node76;
logic [31:0] node77;
logic [31:0] node78;
logic [31:0] node79;
logic [11:0] node80;
logic [31:0] node81;
logic [11:0] node82;
logic [31:0] node83;
logic [11:0] node84;
logic [31:0] node85;
logic [31:0] node86;
logic [31:0] node87;
logic [31:0] node88;
logic [31:0] node89;
logic [31:0] node90;
assign alu_lhs = register_file_read_data1;
assign bus_addr = alu_res;
assign node0 = alu_res;
assign node1 = alu_res;
assign node2 = alu_res;
assign node3 = alu_res;
assign node4 = instruction;
assign node5 = node4[14:12];
assign node6 = instruction;
assign node7 = node6[14:12];
assign bus_byte_enable = ((node7[1:0] == 2'h0) ? ((node2[1:0] == 2'h3) ? 4'h8 : ((node1[1:0] == 2'h2) ? 4'h4 : ((node0[1:0] == 2'h1) ? 4'h2 : 4'h1))) : ((node5[1:0] == 2'h1) ? (node3[1] ? 4'hc : 4'h3) : 4'hf));
assign node8 = instruction;
assign bus_read_req = ((node8[6:2] == 5'h0) ? 1'h1 : 1'h0);
assign node9 = instruction;
assign node10 = instruction;
assign alu_op = ((node10[6:2] == 5'h8) ? 3'h0 : ((node8[6:2] == 5'h0) ? 3'h0 : node9[14:12]));
assign node11 = instruction;
assign node12 = instruction;
assign node13 = instruction;
assign node14 = node13[6:2];
assign node15 = instruction;
assign node16 = instruction;
assign alu_op_mod = ((node10[6:2] == 5'h8) ? 1'h0 : ((node8[6:2] == 5'h0) ? 1'h0 : (~node14[3] ? (((node15[14:12] == 3'h1) | (node16[14:12] == 3'h5)) ? node11[30] : (node14[3] ? node12[30] : 1'h0)) : (node14[3] ? node12[30] : 1'h0))));
assign node17 = instruction;
assign node18 = instruction;
assign node19 = instruction;
assign node20 = instruction;
assign node21 = instruction;
assign node22 = instruction;
assign node23 = instruction;
assign node24 = instruction;
assign node25 = instruction;
assign node26 = instruction;
assign node27 = instruction;
assign alu_rhs = ((node10[6:2] == 5'h8) ? {{{20{node17[31]}}, node18[31:25]}, node19[11:7]} : ((node8[6:2] == 5'h0) ? {{20{node20[31]}}, node21[31:20]} : ((node27[6:2] == 5'h19) ? {{20{node22[31]}}, node23[31:20]} : (~node14[3] ? (((node15[14:12] == 3'h1) | (node16[14:12] == 3'h5)) ? {27'h0, node24[24:20]} : {{20{node25[31]}}, node26[31:20]}) : register_file_read_data2))));
assign node28 = register_file_read_data2;
assign node29 = register_file_read_data2;
assign node30 = register_file_read_data2;
assign node31 = register_file_read_data2;
assign node32 = alu_res;
assign node33 = instruction;
assign node34 = node33[14:12];
assign node35 = alu_res;
assign node36 = alu_res;
assign node37 = alu_res;
assign node38 = instruction;
assign node39 = node38[14:12];
assign bus_write_data = ((node10[6:2] == 5'h8) ? ((node39[1:0] == 2'h0) ? ((node37[1:0] == 2'h3) ? {node28[7:0], 24'h0} : ((node36[1:0] == 2'h2) ? {{8'h0, node29[7:0]}, 16'h0} : ((node35[1:0] == 2'h1) ? {{16'h0, node30[7:0]}, 8'h0} : ((node34[1:0] == 2'h1) ? (node32[1] ? {node31[15:0], 16'h0} : register_file_read_data2) : register_file_read_data2)))) : ((node34[1:0] == 2'h1) ? (node32[1] ? {node31[15:0], 16'h0} : register_file_read_data2) : register_file_read_data2)) : register_file_read_data2);
assign bus_write_req = ((node10[6:2] == 5'h8) ? 1'h1 : 1'h0);
assign node40 = instruction;
assign node41 = instruction;
assign node42 = instruction;
assign node43 = instruction;
assign node44 = instruction;
assign node45 = (pc + {{{{{{19{node40[31]}}, node41[31]}, node42[7]}, node43[30:25]}, node44[11:8]}, 1'h0});
assign node46 = instruction;
assign node47 = instruction;
assign node48 = instruction;
assign node49 = instruction;
assign node50 = instruction;
assign node51 = (pc + {{{{{{11{node46[31]}}, node47[31]}, node48[19:12]}, node49[20]}, node50[30:21]}, 1'h0});
assign node52 = (pc + 32'h4);
assign node53 = instruction;
assign node54 = instruction;
assign node55 = node54[14:12];
assign node56 = instruction;
assign node57 = node56[14:12];
assign node58 = instruction;
assign node59 = node58[14:12];
assign node60 = instruction;
assign node61 = node60[14:12];
assign node62 = instruction;
assign next_pc = ((node62[6:2] == 5'h18) ? ((node61[0] ? ~((node59[2:1] == 2'h3) ? (register_file_read_data1 < register_file_read_data2) : ((node57[2:1] == 2'h2) ? ($signed(register_file_read_data1) < $signed(register_file_read_data2)) : ((node55[2:1] == 2'h0) ? (register_file_read_data1 == register_file_read_data2) : 1'h0))) : ((node59[2:1] == 2'h3) ? (register_file_read_data1 < register_file_read_data2) : ((node57[2:1] == 2'h2) ? ($signed(register_file_read_data1) < $signed(register_file_read_data2)) : ((node55[2:1] == 2'h0) ? (register_file_read_data1 == register_file_read_data2) : 1'h0)))) ? node45[31:0] : ((node27[6:2] == 5'h19) ? alu_res : ((node53[6:2] == 5'h1b) ? node51[31:0] : node52[31:0]))) : ((node27[6:2] == 5'h19) ? alu_res : ((node53[6:2] == 5'h1b) ? node51[31:0] : node52[31:0])));
assign node63 = instruction;
assign node64 = instruction;
assign node65 = instruction;
assign rd_value_write_enable = ((node65[6:2] == 5'h1c) ? ((node64[14:12] == 3'h0) ? 1'h0 : ((node63[6:2] == 5'h3) ? 1'h0 : ((node62[6:2] == 5'h18) ? 1'h0 : ((node10[6:2] == 5'h8) ? 1'h0 : 1'h1)))) : ((node63[6:2] == 5'h3) ? 1'h0 : ((node62[6:2] == 5'h18) ? 1'h0 : ((node10[6:2] == 5'h8) ? 1'h0 : 1'h1))));
assign node66 = instructions_retired_counter_value;
assign node67 = instructions_retired_counter_value;
assign node68 = instruction;
assign node69 = node68[31:20];
assign node70 = cycle_counter_value;
assign node71 = cycle_counter_value;
assign node72 = instruction;
assign node73 = node72[31:20];
assign node74 = instruction;
assign node75 = ({node74[31:12], 12'h0} + pc);
assign node76 = instruction;
assign node77 = instruction;
assign node78 = instruction;
assign node79 = instruction;
assign node80 = node79[31:20];
assign node81 = instruction;
assign node82 = node81[31:20];
assign node83 = instruction;
assign node84 = node83[31:20];
assign node85 = instruction;
assign node86 = instruction;
assign node87 = instruction;
assign node88 = instruction;
assign node89 = instruction;
assign node90 = instruction;
assign rd_value_write_data = ((node65[6:2] == 5'h1c) ? (((((((node85[14:12] == 3'h1) | (node86[14:12] == 3'h2)) | (node87[14:12] == 3'h3)) | (node88[14:12] == 3'h5)) | (node89[14:12] == 3'h6)) | (node90[14:12] == 3'h7)) ? ((node84[1:0] == 2'h2) ? (node69[7] ? node66[63:32] : node67[31:0]) : (((node80[1:0] == 2'h0) | (node82[1:0] == 2'h1)) ? (node73[7] ? node70[63:32] : node71[31:0]) : ((node27[6:2] == 5'h19) ? node52[31:0] : ((node53[6:2] == 5'h1b) ? node52[31:0] : ((node78[6:2] == 5'h5) ? node75[31:0] : ((node77[6:2] == 5'hd) ? {node76[31:12], 12'h0} : alu_res)))))) : ((node27[6:2] == 5'h19) ? node52[31:0] : ((node53[6:2] == 5'h1b) ? node52[31:0] : ((node78[6:2] == 5'h5) ? node75[31:0] : ((node77[6:2] == 5'hd) ? {node76[31:12], 12'h0} : alu_res))))) : ((node27[6:2] == 5'h19) ? node52[31:0] : ((node53[6:2] == 5'h1b) ? node52[31:0] : ((node78[6:2] == 5'h5) ? node75[31:0] : ((node77[6:2] == 5'hd) ? {node76[31:12], 12'h0} : alu_res)))));
endmodule
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