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@DigitalBrains1
DigitalBrains1 / ClockScale.hs
Last active Aug 16, 2018
An UART in CλaSH v0.7
View ClockScale.hs
{-# LANGUAGE DeriveGeneric #-}
{-# LANGUAGE DeriveAnyClass #-}
{-
- Copyright (c) 2015, 2017 Peter Lebbing <peter@digitalbrains.com>
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
@DigitalBrains1
DigitalBrains1 / Toolbox.json
Created Jun 13, 2017
Blackbox spec for dual-port block RAM
View Toolbox.json
[ { "BlackBox" :
{ "name" : "Toolbox.Blockram2p.blockram2p'"
, "type" :
"blockram2p' :: ( BitPack a -- LIT[0]
, BitPack b -- LIT[1]
, KnownNat (BitSize a) -- LIT[2]
, KnownNat (BitSize b) -- LIT[3]
, KnownNat logaw -- LIT[4]
, KnownNat logbw -- LIT[5]
, KnownNat aaw -- LIT[6]
View gist:2ecb7fc2bdcdfe56c16e060e14314680
-- fold begin
fold : block
-- given a level and a depth, calculate the corresponding index into the
-- intermediate array
function depth2index (levels,depth : in natural) return natural is
begin
return (2 ** levels - 2 ** depth);
end function;
signal intermediate : main_types.array_of_boolean(0 to (2*10)-2);
View gist:b867c835212cf2de31ad94e714374580
Computer Information:
Manufacturer: Unknown
Model: Unknown
Form Factor: Desktop
No Touch Input Detected
Processor Information:
CPU Vendor: GenuineIntel
CPU Family: 0x6
CPU Model: 0x3c
@DigitalBrains1
DigitalBrains1 / sailfish-syncevolution.spec
Created Aug 30, 2016
Modified spec file for Sailfish syncevolution
View sailfish-syncevolution.spec
Name: syncevolution
Summary: SyncEvolution - a SyncML and CalDAV/CardDAV client
Version: 1.3.99.7
Release: 1
License: GPL
Source: syncevolution-%{version}-%{release}.tar.gz
BuildRequires: gettext glib2-devel boost-devel pcre-devel cppunit-devel
BuildRequires: libcurl-devel sqlite-devel libxml2-devel openssl-devel zlib-devel
BuildRequires: mkcal-qt5-devel kcalcore-qt5-devel libical-devel
BuildRequires: libaccounts-glib-devel libsignon-glib-devel dbus-glib-devel
@DigitalBrains1
DigitalBrains1 / syncevolution-buildlog
Created Aug 30, 2016
Internal compiler error building syncevolution for Sailfish
View syncevolution-buildlog
[mersdk@SailfishSDK ~]$ cd /home/src1/src/sailfish/syncevolution
[mersdk@SailfishSDK syncevolution]$ mkdir rpm
[mersdk@SailfishSDK syncevolution]$ cp ../sailfish-syncevolution.spec rpm
[mersdk@SailfishSDK syncevolution]$ mb2 -t SailfishOS-armv7hl build
The following NEW packages are going to be installed:
boost-chrono boost-date-time boost-devel boost-graph boost-iostreams boost-locale
boost-math boost-program-options boost-python boost-random boost-regex
boost-serialization boost-signals boost-test boost-thread boost-timer boost-wave
cppunit cppunit-devel cvs dbus-glib-devel gettext gettext-devel gettext-libs
@DigitalBrains1
DigitalBrains1 / gist:63a9ea08597b890b0599
Created Jul 18, 2015
Kernel dmesg: failed to bring up CPU
View gist:63a9ea08597b890b0599
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 3.16.0-4-amd64 (debian-kernel@lists.debian.org) (gcc version 4.8.4 (Debian 4.8.4-1) ) #1 SMP Debian 3.16.7-ckt11-1 (2015-05-24)
[ 0.000000] Command line: BOOT_IMAGE=/vmlinuz-3.16.0-4-amd64 root=/dev/mapper/tweek-root ro
[ 0.000000] e820: BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000be34efff] usable
View keybase.md

Keybase proof

I hereby claim:

  • I am digitalbrains1 on github.
  • I am digitalbrains (https://keybase.io/digitalbrains) on keybase.
  • I have a public key whose fingerprint is 8FA9 4E79 AD6A B56E E38C E5CB AC46 EFE6 DE50 0B3E

To claim this, I am signing this object:

@DigitalBrains1
DigitalBrains1 / wpa_supplicant.spec.patch
Created Apr 11, 2014
Sailfish wpa_supplicant revert commit 51e3eaf: specfile patch
View wpa_supplicant.spec.patch
--- wpa_supplicant.spec.orig 2014-04-09 02:27:47.000000000 +0200
+++ wpa_supplicant.spec 2014-04-11 22:17:01.073543498 +0200
@@ -20,6 +20,7 @@
Patch4: wpa_supplicant-openssl-more-algs.patch
Patch5: wpa_supplicant-gui-qt4.patch
Patch6: libnl3-includes.patch
+Patch7: wpa_supplicant-dont-fail-client-cert.patch
BuildRequires: pkgconfig(libnl-3.0)
BuildRequires: pkgconfig(dbus-1)
BuildRequires: pkgconfig(openssl)
@DigitalBrains1
DigitalBrains1 / wpa_supplicant-dont-fail-client-cert.patch
Last active Aug 29, 2015
Sailfish wpa_supplicant revert commit 51e3eaf: patch
View wpa_supplicant-dont-fail-client-cert.patch
diff -Npru wpa_supplicant-2.1.orig/hostap/src/crypto/tls.h wpa_supplicant-2.1/hostap/src/crypto/tls.h
--- wpa_supplicant-2.1.orig/hostap/src/crypto/tls.h 2014-03-13 08:53:26.000000000 +0100
+++ wpa_supplicant-2.1/hostap/src/crypto/tls.h 2014-04-11 21:50:52.159397490 +0200
@@ -41,8 +41,7 @@ enum tls_fail_reason {
TLS_FAIL_ALTSUBJECT_MISMATCH = 6,
TLS_FAIL_BAD_CERTIFICATE = 7,
TLS_FAIL_SERVER_CHAIN_PROBE = 8,
- TLS_FAIL_DOMAIN_SUFFIX_MISMATCH = 9,
- TLS_FAIL_SERVER_USED_CLIENT_CERT = 10
+ TLS_FAIL_DOMAIN_SUFFIX_MISMATCH = 9
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