NP95

My Vim-related gists

Long-form

• How to use Tim Pope's Pathogen
• Idiomatic vimrc (superseded by idiomatic-vimrc)
• Clipboard sharing on Mac OS X is easy
• Apprentice — The Making Of
• Vim: pushing built-in features beyond their limits
• The right way to override any highlighting if you don't want to edit the colorscheme file directly

NP95

#define VERBOSE1  1 // for debug

// Code for I2C interface.
#include <Wire.h>

// The red LED is controlled by pin 13.
#define RED_LED 13

//Retimer Address
#define Retimer_WriteAddress_0 0x18

NP95

#ifndef __SORT_DFS_H__
#define __SORT_DFS_H__

#include <iostream>
#include <map>
#include <list>

using namespace std;

// G is your graph type

NP95

Quite a bit of latency sensitive work has been moved off software into hardware - mostly FPGA(What is an FPGA?) or to a lesser extent ASIC (Application-specific integrated circuit). They offer the benefit of operating at wire speed. However they are expensive in terms of development and maintenance effort among others. And poorly implemented FPGA based solutions are a nightmare to maintain - especially ones implemented in C using tools like Vivado High-Level Synthesis.

So there is still (for now) a fairly large market for low latency solutions in software. There are no specific requirements per se for low latency programming - you just need a good, solid engineering mindset geared toward methodically getting the best performance. And when you say performance, there are the big 4 metrics -

Throughput
Efficiency
Latency
Jitter
Your focus on the low latency space will be on latency and jitter. Which can be a challenge, because most engineers are trained to focus on throughput and efficiency. And low latency so

NP95

It really depends with whom you will talk and how advance they are in utilising FPGAs in company’s framework. Remember that the big picture is the software framework and the way FPGAs fit in that picture. Question will depend with whom you will talk and with what part of the system they are dealing. You can end up talking with pure hardware engineers (EE), pure software guys that never touch hardware or hw-sw people that i.e. know how SW talks with HW but never optimised HW. It’s really a mixture but it’s worth to remember that it’s dominated by a SW people and FPGAs are usually seen as add-ons.

In general the way it works is that trader (statistician?) creates equation that is transformed into algorithm that is fed into the framework. Framework provides with the book that reflects current stock market and allows for orders execution. Algorithm monitors the book and when finds signal sends orders. To this end, from architectural point of view framework has two aims: a) achieve low latency with high throughpu

NP95

While there are plenty of questions that can be targeted for the candidates however we cannot describe all here. I'm listing most frequent ones

Okay, so as request by few, I shall provide some simple answers here-in

What is speed grade and how do you select FPGA as per requirements
Speed Grade is what that determines how max a clock can run in FPGA. Companies use different values, while -1, -2 indicates the scale. Higher the grade, higher the cost of FPGA
What is the maximum possible speed achievable for a given device say Virtex6 device (some speed grade)
The Fmax is determined by Flop-to-Flop timing using shortest route (CLB) with least clock skew. To put it simple, usually this is calculated based on logic levels between a source to destination path
What is logic level
Number of logics levels in your combo circuit. Google for more info

NP95

First install:

$sudo apt-get install avrdude gcc-avr avr-libc

Then:

$avr-gcc -Os -DF_CPU=16000000UL -mmcu=atmega328p -c -o led.o led.c

-DF_CPU is the CPU clock speed

NP95

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