paniq

#   register allocation algorithm idea in O(n)

    by leonard ritter

    based on DAG visualization here:

    https://twitter.com/paniq/status/1297661746832973825

using import Array

erincandescent

Foreward

This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.

It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.

Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2

Original Foreword: Some Opinion

The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and

paniq

> You'll really have to explain what you are up to, because it's been months we see experiments of yours 
> doing ??? arithmetic, but we still don't know what any of these things are. man :) Would you write 
> somewhere what all these graphs are about? Please....? ^__^

Oh this is just to confuse y'all, there's no point to any of this.

Just kidding.

The point of my XYZ-arithmetic prototypes is to explore & explain various techniques to speed up root finding
over simple sphere tracing, that is, find the surface that a ray hits much faster than SDF's do, but keep