apritzel

		bus_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-h3-bus-gates-clk", "allwinner,sunxi-bus-gates-clk";
			reg = <0x01c20060 0x14>;
			ahb1_parent {
			  clocks = <&ahb1>;
			  clock-indices = <5>, <6>, <8>, ....
			  clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", ...
			};
			apb1_parent {

apritzel

/dts-v1/;

/memreserve/	0x0000000045000000 0x0000000000200000;
/memreserve/	0x0000000041010000 0x0000000000010800;
/memreserve/	0x0000000040100000 0x0000000000006000;
/ {
	model = "Pine64+";
	compatible = "pine64,pine64_plus", "allwinner,a64";
	interrupt-parent = <0x1>;
	#address-cells = <0x1>;

apritzel

diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 69bca18..ea60646 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -143,7 +143,7 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
  * Check if there was a change in the timer state (should we raise or lower
  * the line level to the GIC).
  */
-static void kvm_timer_update_state(struct kvm_vcpu *vcpu)
+static int kvm_timer_update_state(struct kvm_vcpu *vcpu)

apritzel

HELLO! BOOT0 is starting!
boot0 commit : 045061a8bb2580cb3fa02e301f52a015040c158f
 
boot0 version : 4.0.0
set pll start
set pll end
rtc[0] value = 0x00000000
rtc[1] value = 0x00000000
rtc[2] value = 0x00000000
rtc[3] value = 0x00000000

apritzel

diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c
index eb043b1..34f1c6e 100644
--- a/plat/sun50iw1p1/bl31_sunxi_setup.c
+++ b/plat/sun50iw1p1/bl31_sunxi_setup.c
@@ -190,6 +190,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * present.
 	 */
 	sunxi_security_setup();
+
+	sunxi_power_setup();

apritzel

/*
 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,

apritzel

|  BROM  | SRAM A1|    |    SRAM A2      |    |     D R A M  ....
+--------+--------+-||-+--------+--------+-||-+----------+-||-+----------
|boot ROM| boot0  |    |  excp. |  SCP   |    |  ATF     |    | U-Boot
|        |       -------->vec- ===>      |    |          |    |
|      ====>      |    |  tors  |        |    |       ====ERET==>
|        |       =================RMR===========>        |    |
|A32/mon |A32/mon |    |        |  or1k  |    | A64/EL3  |    | A32/svc
+--------+--------+-||-+--------+--------+-||-+----------+-||-+----------
0       64K      96K  256K     272K          1024M          1184M

apritzel

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <inttypes.h>
#include <stdbool.h>
#include <fcntl.h>
#include <errno.h>
#include <unistd.h>
#include <getopt.h>
#include <sys/mman.h>

apritzel

From fbf6111be9ee89afb1a0c47363693dbab96b7d50 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 28 Jul 2016 21:52:51 +0100
Subject: [PATCH] net: sun8i-emac: fix endianness issues

The network MAC in recent Allwinner SoCs uses an internal DMA controller,
which gets its information from DMA descriptors in normal memory.
The device expects the values in there to be in little-endian format.
Since we use normal memory accesses to fill those DMA descriptors, we
must wrap write accesses to these descriptors with cpu_to_le32() calls

apritzel

/*
 * Copyright (C) 2016 ARM Ltd.
 * based on the Allwinner H3 dtsi:
 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *