OpenSTA is an open-source STA tool by Parallax (hence a.k.a. Parallax STA/Static Timing Analyzer). User Manual is part of the repository.
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/ verilog_dependencies.rst
Last active
May 4, 2024 11:10
Discovering Verilog files dependencies #verilog #systemverilog #verilog-perl
The Verilog-perl module comes with some utilities to help you orient yourself in an alien code.
One of the first things you normally do is to understend the module dependencies. That is, what module instantiates other modules. You can do this easily as follows:
vhier -sv --no-missing --missing-modules --forest <files>
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/ sta_data_checks.rst
Last active
May 4, 2024 11:09
STA of data-to-data constraints (or non-sequential timing arcs). #sta #non_seq
STA's primary function is to check a data signal timing to a clock signal timing, such as setup and hold constraints that require the data signal to remain stable around the active clock edge. In certain cases, we need to constrain the data change not to a clock event but another data signal event. These are called data-to-data checks. You can find them frequently in hard macros with asynchronous interfaces; but also in flip-flops with both asynchronous set and reset to enforce priority of one over the other.
Data-to-data checks can be expressed as user constraints (set_data_check) or as Liberty timing arcs
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/ sta_cdc_paths.rst
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May 4, 2024 10:52
Timing constraints for clock-domain crossings. #sta #cdc
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/ sta_pll_example.rst
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March 27, 2024 21:23
Discuss constraining PLL generated clocks in modern STA tools. #sta #pll
Phase-Locked Loop (PLL) is used to compensate delay in its feedback path, which can be used for different purposes. The most frequent uses are to compensate the clock tree delay/depth or to compensate the IO delay (or both).
A decade ago, accounting for the compensation in STA timing used to be a haedache. See P. Zimmer. Working with PLLs in PrimeTime – avoiding the phase locked oops, SNUG San Jose 2005, http://www.zimmerdesignservices.com/mydownloads/zimmer_pll_update_051405.pdf
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/ huddle_usage.rst
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March 14, 2024 15:21
Using Tcl Huddle serialization format. #tcl #huddle
Tcllib's ::huddle is a native serialization format and is part of its YAML package. ::huddle's function is the same as of JSON or YAML; that is to augment commond data types along with the data. When JSON or YAML get parsed into an interpretter, individual data get represented by its native type; that is, string becomes a string, list becomes a list, map becomes a map/hash/dictionary, etc.
In Tcl, the problem is that all these types are mostly interchangeble (which is normally
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/ riscv_debug_module_v11.md
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February 20, 2024 13:04
Describes implementation of RISC-V Debug Module (primarily as per Debug Spec. v0.11).
This gist discusses implementation of a Debug Module (DM) primarily per RISC-V Debug Specification v0.11. The core ideas, though, apply to Debug Specification v0.13. Information presented here come from various sources, but mostly from Debug Specs, riscv-isa-sim and from reverse engineering e200_opensource. Relevant source of information is also riscv-openocd.
RISC-V Foundation established a debug task group to propose and standardize mechanisms for external debugging of RISC-V (RV) cores. This effort resulted in drafting a RISC-V External Debug Supprt specification, early [v0.1
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/ _sta_async_counter.md
Last active
February 2, 2024 00:40
Shows how to constrain an asynchronous counter. #sta #doc
This work is licensed under a Creative Commons Attribution 4.0 International License.
[1] Why am I Getting UITE-461 Messages and Zero Source Latency?, Solvent article No. 020373, last modified 12/13/2016, https://solvnet.synopsys.com/retrieve/020373.html
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/ custom_coverpage.rst
Created
January 28, 2024 20:06
Custom cover page with LaTeX memoir class.
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