buttercutter

module Tx_TOP(clk, reset, start, i_data, serial_out)   // UART transmitter :  parallel input, serial output

input clk;  // 48MHz
input reset;
input start;     // i_data is valid, so start transmission
input[7:0] i_data;
output serial_out;

wire baud_out;  // 16*baudrate clock
wire serial_data;  // output from serializer (TxUART)

buttercutter

#include <verilated.h>          // Defines common routines
//#include <verilatedos.h>
#include "VTx_top.h"

#include "verilated_vcd_c.h"

#include <iostream>
#include <string>
#include <cstdlib>
#include <cstdio>

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// -*- mode: C++; c-file-style: "cc-mode" -*-
//=============================================================================
//
// THIS MODULE IS PUBLICLY LICENSED
//
// Copyright 2001-2017 by Wilson Snyder.  This program is free software;
// you can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
//
// This is distributed in the hope that it will be useful, but WITHOUT ANY

buttercutter

`ifdef VERILATOR
	`define SIMULATION   // for verilator simulation only
`endif

module Tx_top
(clk,
`ifdef SIMULATION
	start, i_data,
`endif
serial_out);   // UART transmitter :  parallel input, serial output (PISO)

buttercutter

module Rx_top(clk, serial_in, received_data, rx_error, data_is_available, data_is_valid);  // serial input, parallel output

input clk, serial_in;
output reg rx_error, data_is_available, data_is_valid;
output reg [7:0] received_data;

// determines when to sample data
RxUART rx (.clk(clk), .serial_in(serial_in), .data_is_available(data_is_available), .data_is_valid(data_is_valid), .rx_error(rx_error));

// handles data sampling

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module RxUART(clk, serial_in, data_is_available, data_is_valid);  // manages UART Rx deserializer-related control signal

input clk, serial_in;
output reg data_is_available; // if asserted HIGH, it is ok to sample the serial_in
output reg data_is_valid;   // all 8-bit data have been sampled, please note that valid does not mean no data corruption

wire start_detected; // start_bit is detected
wire is_parity_stage;  // is the parity bit being received now ?
wire sampling_strobe; // determines when to sample the incoming Rx

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module check_parity(clk, serial_in, received_data, data_is_valid, is_parity_stage, rx_error); // even parity checker

input clk, serial_in, data_is_valid, is_parity_stage;
input [7:0] received_data;
output reg rx_error = 0; 

reg parity_value; // this is being computed from the received 8-bit data
reg parity_bit;  // this bit is received directly through UART

always @(posedge clk)

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module rx_state(clk, start_detected, sampling_strobe, data_is_available, data_is_valid, is_parity_stage);  // FSM for UART Rx

input clk, start_detected, sampling_strobe;
output reg data_is_available = 0;
output reg data_is_valid = 0;
output reg is_parity_stage = 0;

reg [3:0] state = 0;

localparam Rx_IDLE       = 4'b0000

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module sampling_strobe_generator(clk, start_detected, sampling_strobe);  // produces sampling control signal for the incoming Rx

input clk, start_detected;
output reg sampling_strobe = 0;

localparam CLOCKS_PER_BIT = 5000; // number of system clock in one UART bit, or equivalently 1/9600Hz divided by 1/48MHz

reg [($clog2(CLOCKS_PER_BIT)-1) : 0] counter = 0;

always @(posedge clk)

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module shift_register(clk, serial_in, data_is_available, received_data);  // manages sampling-related data signal using SIPO shift register

input clk, serial_in, data_is_available;
output reg [7:0] received_data; // SIPO

always @(posedge clk)
begin
    if(data_is_available)
    	received_data <= { serial_in , received_data[7:1] };  // LSB received first by UART definition
end