drhelius

#!/bin/bash

input_filepath="image.png"
output_iconset_name="iconfile.iconset"
mkdir $output_iconset_name

sips -z 16 16     $input_filepath --out "${output_iconset_name}/icon_16x16.png"
sips -z 32 32     $input_filepath --out "${output_iconset_name}/icon_16x16@2x.png"
sips -z 32 32     $input_filepath --out "${output_iconset_name}/icon_32x32.png"
sips -z 64 64     $input_filepath --out "${output_iconset_name}/icon_32x32@2x.png"

drhelius

                          THE ISA AND PC/104 BUS



IBM, IBM/XT, IBM PC, and IBM PC AT are registered trademarks of 
International Business Machines Corporation.

This file is designed to give a basic overview of the bus found in
most IBM clone computers, often referred to as the XT or AT bus. The 
AT version of the bus is upwardly compatible, which means that cards

drhelius

Interrupt INT 48h - LCD STAT
----------------------------


The STAT register (FF41) selects the conditions that will generate this
interrupt (expecting that interrupts are enabled via EI or RETI and that
IE.1 (FFFF.1) is set).
  STAT.3        HBLANK  (start of mode 0)
  STAT.4        VBLANK  (start of mode 1) (additional to INT 40)
  STAT.5        OAM     (start of mode 2 and mode 1)

drhelius

MEMPTR, esoteric register of the ZiLOG Z80 CPU.
by Boo-boo (first and draft English translation by Vladimir Kladov)

  As it is known, after the instruction BIT n,(HL) execution, bits 3 and 5 of the flag register become containing values that is not documented in the official documentation at all. Actually these bits are copied from the bits 11 and 13 of the internal register pair of Z80 CPU, which is used for 16-bit operations, and in most cases to handle addresses. This is usual practice for processors having 8-bits data bus working with 16-bits data.
  It is not known why and how these bits of the internal buffer register are copied to the flags register though. At least Sean Young in the "Undocumented Z80 Documented" refers to that phenomenon (http://www.myquest.nl/z80undocumented/) and a bit more info can be found in the Z80 description of another "nocash" project (http://www.work.de/nocash/zxdocs.htm) where such register pair is called as MEMPTR. Unfortunately until now attemts to crack the algorithm se

drhelius

MBC3 RTC save format

the RTC data is appended after the sav file, 44 or 48 bytes. you can detect its presence by the save data being 44 or 48 bytes bigger than the cart's ram size, or 44 or 48 bytes bigger than a multiple of 8192.

old VBA (from 2005) saves the 44 bytes version, and can load both the 44 and 48 bytes version.

VBA-M saves the 48 bytes version, and can *only* load the 48 bytes version.

one should load both types, and always save the 48 bytes version.

drhelius

	LD SP,$fffe		; $0000  Setup Stack

	XOR A			; $0003  Zero the memory from $8000-$9FFF (VRAM)
	LD HL,$9fff		; $0004
Addr_0007:
	LD (HL-),A		; $0007
	BIT 7,H		; $0008
	JR NZ, Addr_0007	; $000a

	LD HL,$ff26		; $000c  Setup Audio

drhelius

; GameBoy Color Boot ROM Disassembly
; Dumped by Costis
; Commenting by Randy Mongenel (Duo)
; WORK-IN-PROGRESS VERSION 09-27-2009

; ===========================================================================

; Segment type:	Pure code
		SECTION	"ROM", CODE

drhelius

1.01 - Added some new licensees, fixed some
        descriptions.
v1.00 - Initial release.
_______________

This information was taken and compiled from Martin Korth's
NO$GMB emulator. Best viewed in DOS EDIT.

Every Gameboy ROM header starts off at the HEX offset 0134.

drhelius

Memory Bank Controller (MBC) 3 for GameBoy Information



            by bRILLO hEAD, 1-Jan-98



 The MBC3 is a memory controller for some GameBoy carts

drhelius

Nitty Gritty Gameboy Cycle Timing
                  ---------------------------------
                  
                  
A document about the down and dirty timing of the Gameboy's video hardware.

Written by:  Kevin Horton
Version: 0.01 (preliminary)

My findings here are based on the original DMG, Super Gameboy, and GB