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## DSM.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity DSM is
    Port ( Clk : in  STD_LOGIC;
           SignalOut : out  STD_LOGIC;
           SignalIn : in  STD_LOGIC_VECTOR (9 downto 0));
	library IEEE;
	use IEEE.STD_LOGIC_1164.ALL;
	use IEEE.STD_LOGIC_UNSIGNED.ALL;
	use IEEE.STD_LOGIC_ARITH.ALL;


	entity DSM is
	Port ( Clk : in STD_LOGIC;
	SignalOut : out STD_LOGIC;
	SignalIn : in STD_LOGIC_VECTOR (9 downto 0));