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Marius Gedminas mgedmin

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View dram_latency_then_and_now.md

One thing that surprises newer programmers is that the older 8-bit microcomputers from the 70s and 80s were designed to run at the speed of random memory access to DRAM and ROM. The C64 was released in 1982 when I was born and its 6502 CPU ran at 1 MHz (give or take depending on NTSC vs PAL). It had a 2-stage pipelined design that was designed to overlap execution and instruction fetch for the current and next instruction. Cycle counting was simple to understand and master since it was based almost entirely on the number of memory accesses (1 cycle each), with a 1-cycle penalty for taken branches because of the pipelined instruction fetch for the next sequential instruction. So, the entire architecture was based on keeping the memory subsystem busy 100% of the time by issuing a read or write every cycle. One-byte instructions with no memory operands like INX still take the minimum 2 cycles per instruction and end up redundantly issuing the same memory request two cycles in a row.

View gist:457dfe5cb1f2b9d8600b
---
- hosts: all
sudo: true
vars_files:
- vars.yml
vars:
body:
name: "{{host_variable}}"
tasks:
- uri:
@mgedmin
mgedmin / mako_tb.py
Created Dec 12, 2012 — forked from anonymous/mako_tb.py
Fixing Mako tracebacks (version 1)
View mako_tb.py
import linecache
import traceback
import sys
import mako.template
def mako_error_handler(context, error):
"""Decorate tracebacks when Mako errors happen.
Evil hack: walk the traceback frames, find compiled Mako templates,
stuff their (transformed) source into linecache.cache.