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diff --git a/fusesoc/section.py b/fusesoc/section.py | |
index 3026b86..39c1da8 100644 | |
--- a/fusesoc/section.py | |
+++ b/fusesoc/section.py | |
@@ -5,6 +5,26 @@ from fusesoc.utils import pr_warn, pr_info, unique_dirs | |
from fusesoc.vlnv import Vlnv | |
class File(object): | |
+ FILE_TYPES = [ | |
+ 'QIP', |
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import os | |
import signal | |
import subprocess | |
import time | |
subprocess.call(['fusesoc', 'sim', '--sim=verilator', '--build-only', 'mor1kx-generic']) | |
apps = [ | |
'or1k-alignillegalinsn', | |
'or1k-backtoback_jmp', |
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import logging | |
import os.path | |
import subprocess | |
import sys | |
if sys.version[0] == '2': | |
import ConfigParser as configparser | |
else: | |
import configparser |
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`default_nettype none | |
module m(output wire a, input wire b); | |
assign `A = b; | |
endmodule |
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module cnt1 | |
#(parameter dw = 32, | |
parameter val = 100) | |
(input clk, | |
output reg en = 1'b0); | |
reg [dw-1:0] cnt = 'd0; | |
always @(posedge clk) begin | |
cnt <= cnt + 1'd1; |
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parameters: | |
clk_freq: 10000000 | |
baud_rate : 19500 | |
vlnv : ::uart:0 |
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[options] | |
mode prove | |
depth 10 | |
[engines] | |
smtbmc | |
[script] | |
read_verilog -formal ror.v | |
prep -top ror |
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`default_nettype none | |
module serv_uart_rx | |
( | |
input wire i_clk, | |
input wire i_wb_cyc, | |
output reg [7:0] o_wb_rdt, | |
output wire o_wb_ack, | |
input i_rx); |
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from sympy.logic import SOPform | |
from sympy import symbols | |
a, w, x, y, z = symbols('opcode[4] opcode[3] opcode[2] opcode[1] opcode[0]') | |
dontcares = [ | |
# [0, 0, 0, 0, 0], | |
[0, 0, 0, 0, 1], | |
[0, 0, 0, 1, 0], | |
[0, 0, 0, 1, 1], | |
# [0, 0, 1, 0, 0], |
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