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dependencies:
  ::serv:1.0.2: []
  ::servant:1.0.2:
  - ::serv:1.0.2
files:
- core: ::serv:1.0.2
  file_type: verilogSource
  is_include_file: true
  name: ../src/serv_1.0.2/rtl/serv_params.vh
- core: ::serv:1.0.2

olofk

#!/usr/bin/python
import os
import subprocess
import sys

containers = {
    'flow.tcl'     : 'edalize/openlane-sky130:v0.12',
    'yosys'        : 'hdlc/yosys',
    'nextpnr-ice40': 'hdlc/nextpnr',
    'nextpnr-ecp5' : 'hdlc/nextpnr',

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set_io q[0] 27
set_io q[1] 25
set_io q[2] 21
set_io q[3] 23
set_io q[4] 26
set_io q[5] 11
set_io q[6] 37

set_io i_clk 35
set_io i_rst 10

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CAPI=2:

name : openc910
description : T-Head Semi OpenC910 RISC-V core

filesets:
  rtl:
    files:
      - C910_RTL_FACTORY/gen_rtl/cpu/rtl/cpu_cfig.h
      - C910_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h

olofk

#!/usr/bin/env python3
import io
import os
import shutil
import sys
import tarfile
import urllib.request

#TODO: Option to override cache dir
xdg_cache_home = os.environ.get("XDG_CACHE_HOME") or os.path.join(

olofk

from sympy.logic import SOPform
from sympy import symbols
from functools import partial, reduce
from itertools import product

HEADER = """module serv_auto_decode 
  (
   input wire i_clk,
   //Input
   input wire i_en,

olofk

module corescore_emitter_uart
  #(
    parameter clk_freq_hz = 0,
    parameter baud_rate = 57600)
  (
   input wire 	    i_clk,
   input wire 	    i_rst,
   input wire [7:0] i_data,
   input wire 	    i_valid,
   output reg 	    o_ready,

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`default_nettype none

module serv_top
  #(parameter WITH_CSR = 1,
    parameter PRE_REGISTER = 1,
    parameter RESET_STRATEGY = "MINI",
    parameter RESET_PC = 32'd0)
   (
   input wire 		      clk,
   input wire 		      i_rst,

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dependencies:
  ::serv:1.0.2: []
  ::servant:1.0.2:
  - ::serv:1.0.2
files:
- core: ::serv:1.0.2
  file_type: vlt
  name: ../src/serv_1.0.2/data/verilator_waiver.vlt
- core: ::serv:1.0.2
  file_type: verilogSource

olofk

diff --git a/azadi_rtl_v0.6/registers.svh b/azadi_rtl_v0.6/registers.svh
index c1975ed..779f07e 100644
--- a/azadi_rtl_v0.6/registers.svh
+++ b/azadi_rtl_v0.6/registers.svh
@@ -200,9 +200,9 @@
 // __clk: clock input
 // __arst_n: asynchronous reset
 `define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \
-    `ifndef VERILATOR                       \
-  /``* synopsys sync_set_reset `"__clear`" *``/                       \