rasky

# Helper macros for vector shifts.
# How to use:
#   1) Call macro "vsll_data"/"vsll8_data" in the data segment to define the required constants
#   2) Call macro "setup_vsll <VREG>" / "setup_vsll8 <VREG>" in code, passing in one vreg that will hold shift constants
#   3) You can now use the following macros:
#      * "vsll <VREG-DST>, <VREG-SRC>, <QTY>" to perform a left shift from 0 to 7 bits.
#      * "vsll8 <VREG-DST>, <VREG-SRC>, <QTY>" to perform a left shift from 8 to 15 bits.
#      * "vsrl <VREG-DST>, <VREG-SRC>, <QTY>" to perform a logical (unsigned) right shift from 0 to 7 bits.
#      * "vsrl8 <VREG-DST>, <VREG-SRC>, <QTY>" to perform a logical (unsigned) right shift from 8 to 15 bits.
#      * "vsra <VREG-DST>, <VREG-SRC>, <QTY>" to perform an arithmetic (signed) shift from 0 to 7 bits.

rasky

curl -X POST http://127.0.0.1:31999/order_insert -H "Content-Type: application/json" --data "{\"code\":\"test\", \"model\": \"\\\\flfir01\\Datastore1\\Dept_ModelMaker\\Mozart\\AAMA\\MODELLI CENTRO TAGLIO\\INDUSTRIA 4.0\\prove linda\\SS20 201021 HV TGL.cmz\", \"qty\": [{\"items\": 10}]}"

rasky

--- proved-base-sorted.txt	2018-09-06 00:17:38.000000000 +0200
+++ proved-new-sorted.txt	2018-09-06 08:43:52.000000000 +0200
@@ -986,6 +986,7 @@
 cmd/compile/internal/gc/bv.go:272:13: Proved IsInBounds
 cmd/compile/internal/gc/bv.go:78:4: Proved IsInBounds
 cmd/compile/internal/gc/bv.go:86:4: Proved IsInBounds
+cmd/compile/internal/gc/class_string.go:15:33: Proved IsInBounds
 cmd/compile/internal/gc/closure.go:134:29: Proved IsNonNil
 cmd/compile/internal/gc/closure.go:139:35: Proved IsInBounds
 cmd/compile/internal/gc/closure.go:145:15: Proved IsInBounds

rasky

extern crate num;
extern crate typenum;
use self::num::cast::NumCast;
use self::num::{PrimInt, ToPrimitive};
use self::typenum::{
    IsLessOrEqual, NonZero, True, U0, U1, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19, U2,
    U20, U21, U22, U23, U24, U25, U26, U27, U28, U29, U3, U30, U31, U32, U4, U5, U6, U64, U7, U8,
    U9, Unsigned,
};
use std::fmt;

rasky

> ../src/cmd/compile/internal/gc/timings.go:84:29: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:587:26: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:588:14: Proved IsSliceInBounds
> ../src/cmd/compile/internal/ssa/prove.go:640:55: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:848:29: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:851:18: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:851:29: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:855:18: Proved IsInBounds
> ../src/cmd/compile/internal/ssa/prove.go:857:19: Proved IsInBounds
> ../src/cmd/compile/internal/syntax/parser.go:141:9: Proved IsInBounds

rasky

package abs

import (
	"math/rand"
	"reflect"
	"runtime"
	"strings"
	"testing"
)

rasky

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
                 Starting Crush
                 Version: TestU01 1.2.3
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


***********************************************************
Test smarsa_SerialOver calling smultin_MultinomialOver

***********************************************************

rasky

def is_match(s):
    # '(a[0]+b[2c[6]]) {24 + 53}' -> true
    # 'f(e(d))' -> true
    # '[()]{}([])' -> true
    # '((b)' -> false
    # '(c]' -> false
    # '{(a[])' -> false
    # '([)]' -> false
    # '][' -> false
    # 'a' -> true

rasky

#!/usr/bin/python3
# -*- encoding: utf-8 -*-
import math

N0 = 128   # number of 8-byte ints in intlist before we switch to bloom
E = 0.003  # desired false-positive error rate
P = 0.5    # desired fill ratio
R = 0.85   # tightening ratio
S = 2.0    # growth ratio

rasky

class Traildb < Formula
  desc "Blazingly-fast database for log-structured data"
  homepage "http://traildb.io"
  url "https://github.com/traildb/traildb/archive/0.5.tar.gz"
  sha256 "4d1b61cc7068ec3313fe6322fc366a996c9d357dd3edf667dd33f0ab2c103271"

  depends_on "libarchive"
  depends_on "homebrew/boneyard/judy"
  depends_on "pkg-config" => :build