rescurib

#!/usr/bin/env python3
# -*- coding: utf-8 -*-
"""
Created on Fri Jan 25 17:11:27 2019

@author: Rodolfo E. Escobar U.
"""
from mpl_toolkits.mplot3d import Axes3D  # noqa: F401 unused import
import numpy as np
import matplotlib.pyplot as plt

rescurib

#!/usr/bin/env python3
# -*- coding: utf-8 -*-
"""
Created on Mon Jan 14 20:23:30 2019

@author: Rodolfo Escobar
"""
import matplotlib.pyplot as plt
from matplotlib.ticker import StrMethodFormatter
import numpy as np

rescurib

ORTOFOTO DIGITAL: E14A69E

FUENTE: Fotografías aéreas escala 1:75,000 de Noviembre de 1995
PROCESAMIENTO: Rectificación de fotografías aéreas, con auxilio
de puntos de control geodésico y Modelo Digital de Elevación.
PROYECCION: Universal Transversa de Mercator (UTM)
DATUM: ITRF92
ELIPSOIDE: GRS 80
DIMENSIONES DE LA IMAGEN:
            Columnas : 5950

rescurib

/*
 1) Cada maestro sólo trabaja un dia a la semana 
    y da una sóla materia.
 2) Elisa da programación posterior al dia que se da lógica. 
 3) Carlos no trabaja el lunes, día que no se da lógica.
 */

materia(logica).
materia(programacion).
materia(matematicas).

rescurib

\documentclass[10pt,a4paper]{report}
\usepackage[spanish]{babel}
\deactivatequoting
\usepackage[utf8]{inputenc}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{tikz}
\usetikzlibrary{automata,positioning,arrows} 

rescurib

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

entity divisor is
port ( pulso : inout std_logic:='0';
       clk   : in std_logic);
        
end entity;

rescurib

-- -------------------------------------------------------------
-- 
-- File Name: hdlsrc\Generador_Coseno_HDL\Fixed_Point_Multiplication.vhd
-- Created: 2017-12-01 00:57:53
-- 
-- Generated by MATLAB 8.5 and HDL Coder 3.6
-- 
-- -------------------------------------------------------------

rescurib

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

entity DAC_SPI is

    port(
        clk            : in    std_logic; -- 50 MHz		  
        reset          : in    std_logic;
        datos_entrada  : in    std_logic_vector(15 downto 0);

rescurib

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fixed_mult is
    Port ( ADC : in  STD_LOGIC_VECTOR (11 downto 0);
           DAC : out  STD_LOGIC_VECTOR (11 downto 0));
end fixed_mult;

architecture Behavioral of fixed_mult is

rescurib

-- -------------------------------------------------------------
-- 
-- File Name: hdlsrc\Control_P_Div_HDL\Control_P_Div_HDL.vhd
-- Created: 2017-11-05 22:25:53
-- 
-- Generated by MATLAB 8.5 and HDL Coder 3.6
-- 
-- 
-- -------------------------------------------------------------
-- Rate and Clocking Details