Shashi18

module master(data,address,clk,rw,sda,scl,register,data_wr);

output reg sda;

input [7:0] data;

input [7:0] data_wr;

reg [7:0]data_wr_dup;

Shashi18

module error_detect(input [11:0]in,input clk,input [5:0]p1,p2,input [4:0]p3,p4,output reg [3:0]bit_error,output reg[11:0]k);
reg [3:0]num;
reg [31:0]num1;

//integer bit_error;
initial begin
bit_error = 0;
num1 = $random();
num = num1[31:28];

Shashi18

module D1(Di,Q, Qb, clk, clear);
input Di, clk, clear;
output reg Q, Qb;
initial begin
Q = 0;
Qb = ~Q;
end

always @(posedge clk or negedge clear)begin
	if(~clear)begin

Shashi18

//********D Flip Flop**************//
module D1(Di,Q, Qb, clk, clear);
input Di, clk, clear;
output reg Q, Qb;
initial begin
Q = 0;
Qb = ~Q;
end

always @(posedge clk or posedge clear)begin

Shashi18

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [2:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
  D D2(Qb2, Q2, Qb2, Qb);
  D D3(Qb3, Q3, Qb3, Qb2);
assign Out = {Qb3,Qb2,Qb};
endmodule

Shashi18

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [2:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
D D2(Qb2, Q2, Qb2, Q);
D D3(Qb3, Q3, Qb3, Q2);
assign Out = {Qb3,Qb2,Qb};
endmodule

Shashi18

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [1:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
D2 D2(Qb2, Q2, Qb2, Q);
assign Out = {Qb2,Qb};
endmodule

Shashi18

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [1:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
  D2 D2(Qb2, Q2, Qb2, Qb);
assign Out = {Qb2,Qb};
endmodule

Shashi18

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [1:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
D2 D2(Qb2, Q2, Qb2, Q);
assign Out = {Qb2,Qb};
endmodule

Shashi18

//************8Main Code***************
module Main(input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );
    reg M,N;

always @(posedge clk) begin