Shashi18

module ALU(clk_ALU,ain,bin,func,result,z,carry);
input clk_ALU;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin

Shashi18

module DATAPATH(clk, out, A_reg, B_reg, W_reg, read_data_A, read_data_B, opcode, alu_result, write_data, sel3,carry, z_flag);
input clk;
wire [15:0]instruction;
wire [7:0]sign_out;
wire [7:0]in;
wire [7:0]b_out, in_1, in_2, in_3, in_4;
output [7:0] out;
wire [3:0] Sign, Write_reg;
wire [3:0] aluop; wire [7:0] write_data; wire [7:0] read_data;
wire [7:0]read_data_A, read_data_B, mux2_out, data_out;

Shashi18

module MUX1(a,b,sel,c);

input [3:0] a,b;

input sel;

output reg [3:0]c;

always @(*)begin

Shashi18

module ALU(clk,ain,bin,func,result,z,carry);
input clk;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin

Shashi18

	module INSTRUCTION_MEMORY(address,clk,opcode,A_reg,B_reg,W_reg,Sign);
input [7:0]address;
input clk;
reg [3:0]dest;
output reg [3:0]opcode;
output reg [3:0]A_reg;
output reg [3:0]B_reg;
output reg [3:0]W_reg;
output reg [3:0]Sign;
reg [7:0] imem[0:17];

Shashi18

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        www.Hellocodings.com
// Engineer: 		 Shashi Suman
// 
// Create Date:    17:26:45 12/24/2018 
// Design Name: 	 Slave_Module
// Module Name:    Slave 
// Project Name: 	 I2C Protocol
// Target Devices: Spartan 6

Shashi18

module Master(clk, sda, scl);
input clk;
inout [0:0] sda;
output reg scl;

reg [7:0]register_address = 8'b10101011;
reg scl_flag;
reg [6:0] slave_address;
wire start_flag;
reg status;

Shashi18

module TestJK;







 // Inputs

Shashi18

module tbmast;



            // Inputs

            reg [6:0] address;

            reg [7:0] register;

Shashi18

module slave(out,sda,scl);

input sda;

input scl;

output reg [7:0]out;

integer j = 0;