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import gym | |
import random | |
import numpy as np | |
from numpy import * | |
import math | |
from statistics import median | |
from matplotlib import pyplot as plt | |
from scipy import signal | |
pendulum = gym.make('LunarLander-v2') | |
pendulum.reset() |
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import gym | |
import numpy as np | |
from numpy import * | |
from matplotlib import pyplot as plt | |
import matplotlib.animation as anim | |
from scipy import signal | |
env = gym.make('CartPole-v1') | |
env.reset() | |
import numpy as np |
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5.1,3.5,1.4,0.2,Iris-setosa | |
4.9,3.0,1.4,0.2,Iris-setosa | |
4.7,3.2,1.3,0.2,Iris-setosa | |
4.6,3.1,1.5,0.2,Iris-setosa | |
5.0,3.6,1.4,0.2,Iris-setosa | |
5.4,3.9,1.7,0.4,Iris-setosa | |
4.6,3.4,1.4,0.3,Iris-setosa | |
5.0,3.4,1.5,0.2,Iris-setosa | |
4.4,2.9,1.4,0.2,Iris-setosa | |
4.9,3.1,1.5,0.1,Iris-setosa |
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import numpy as nmpy #Importing Numpy library for matrix operation | |
#Creating a Perceptron Class with training and pocket algorithm testing function | |
class Create_Perceptron(): | |
def __init__(self, vector, weight, label, learning, bias): | |
self.vector = vector | |
self.weight = weight | |
self.labels = label | |
self.current_accuracy = 0 |
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module DataPath_2(clk, reset, current_PC_address,readA_O, readB_O, A_Reg_IF2ID, B_Reg_IF2ID, Sign_IF2ID, opcode, W_Reg_IF2ID, W_address_WB, alu_result_O, W_data_WB); | |
input clk, reset; | |
output [7:0] current_PC_address,readA_O, readB_O; | |
output [3:0] opcode, A_Reg_IF2ID, B_Reg_IF2ID, W_Reg_IF2ID, Sign_IF2ID, W_address_WB; | |
output [7:0] alu_result_O, W_data_WB; | |
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module MUX3(a,b,sel,c); | |
input [7:0] a,b; | |
input sel; | |
output reg [7:0]c; | |
always @(*)begin | |
if(sel==0) | |
c = a; | |
else | |
c = b; | |
end |
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module EXE2WB(clk, WB, mem_out, alu_result, mux1_w_reg, mux1_w_reg_O, alu_O, mem_out_O, mux3, regwrt | |
); | |
input clk; | |
input [1:0] WB; | |
input [7:0] mem_out; | |
input [7:0] alu_result; | |
input [3:0] mux1_w_reg; | |
output reg [3:0] mux1_w_reg_O; | |
output reg [7:0] alu_O, mem_out_O; |
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module ALU(ain,bin,func,result,z,carry); | |
//input clk; | |
input [7:0]ain; | |
input [7:0]bin; | |
output reg [7:0]result; | |
reg [8:0]temp; | |
output reg carry; | |
input [3:0]func; | |
output reg z; | |
initial begin |
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module ADDER(A,B,out); | |
input [7:0] A,B; | |
output reg [7:0] out; | |
reg [7:0] temp; | |
initial begin | |
out <= 0; | |
end | |
always @(*)begin | |
temp = B<<1; | |
out = A + temp - 2; |
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module IF2ID(clk, next_PC_address, opcode, A_Reg, B_Reg, W_Reg, Sign, freeze, flush, | |
next_PC_address_O, opcode_O, A_Reg_O, B_Reg_O, W_Reg_O, Sign_O); | |
input clk; | |
input [7:0] next_PC_address; | |
input [3:0] opcode; | |
input [3:0] A_Reg; | |
input [3:0] B_Reg; | |
input [3:0] W_Reg; | |
input [3:0] Sign; |
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