apritzel

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 80b0a49..0a7865a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -54,28 +54,28 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {

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Rebuilding the firmware image

The Pine64 firmware consists of four parts:

• The on-chip boot ROM (BROM), which cannot be changed and does the very first steps in loading code. It is part of the A64 SoC and thus not included here.
• A secondary program loader (SPL): Its main task is to initialize the DRAM and load the remaining firmware parts. Due to BROM limitations the SPL is limited in size to 32K. The SPL can be a part of U-Boot, but at the moment we lack free source for the DRAM initialization. The alternative is to use Allwinner's boot0, which is a closed source, but redistributable blob serving the same purpose.
• An EL3 runtime firmware. The task of this code is to provide runtime services like PSCI. It stays resident during the whole time and can be called from an OS like Linux to enable or disable secondary cores or request other services. It also takes care of low level CPU initialization and some errata handling. We use a version of ARM Trusted Firmware, based on the official 1.0 release from

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|  BROM  | SRAM A1|    |    SRAM A2      |    |     D R A M  ....
+--------+--------+-||-+--------+--------+-||-+----------+-||-+----------
|boot ROM| boot0  |    |  excp. |  SCP   |    |  ATF     |    | U-Boot
|        |       -------->vec- ===>      |    |          |    |
|      ====>      |    |  tors  |        |    |       ====ERET==>
|        |       =================RMR===========>        |    |
|A32/mon |A32/mon |    |        |  or1k  |    | A64/EL3  |    | A32/svc
+--------+--------+-||-+--------+--------+-||-+----------+-||-+----------
0       64K      96K  256K     272K          1024M          1184M

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/*
 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,

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diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c
index eb043b1..34f1c6e 100644
--- a/plat/sun50iw1p1/bl31_sunxi_setup.c
+++ b/plat/sun50iw1p1/bl31_sunxi_setup.c
@@ -190,6 +190,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * present.
 	 */
 	sunxi_security_setup();
+
+	sunxi_power_setup();

apritzel

HELLO! BOOT0 is starting!
boot0 commit : 045061a8bb2580cb3fa02e301f52a015040c158f
 
boot0 version : 4.0.0
set pll start
set pll end
rtc[0] value = 0x00000000
rtc[1] value = 0x00000000
rtc[2] value = 0x00000000
rtc[3] value = 0x00000000

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diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 69bca18..ea60646 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -143,7 +143,7 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
  * Check if there was a change in the timer state (should we raise or lower
  * the line level to the GIC).
  */
-static void kvm_timer_update_state(struct kvm_vcpu *vcpu)
+static int kvm_timer_update_state(struct kvm_vcpu *vcpu)

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/dts-v1/;

/memreserve/	0x0000000045000000 0x0000000000200000;
/memreserve/	0x0000000041010000 0x0000000000010800;
/memreserve/	0x0000000040100000 0x0000000000006000;
/ {
	model = "Pine64+";
	compatible = "pine64,pine64_plus", "allwinner,a64";
	interrupt-parent = <0x1>;
	#address-cells = <0x1>;

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		bus_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-h3-bus-gates-clk", "allwinner,sunxi-bus-gates-clk";
			reg = <0x01c20060 0x14>;
			ahb1_parent {
			  clocks = <&ahb1>;
			  clock-indices = <5>, <6>, <8>, ....
			  clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", ...
			};
			apb1_parent {

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HELLO! BOOT0 is starting!
boot0 commit : 045061a8bb2580cb3fa02e301f52a015040c158f
 
boot0 version : 4.0.0
set pll start
set pll end
rtc[0] value = 0x00000000
rtc[1] value = 0x00000000
rtc[2] value = 0x00000000
rtc[3] value = 0x00000000