Navigation Menu

Skip to content

Instantly share code, notes, and snippets.

@cellularmitosis
Last active October 4, 2020 01:26
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save cellularmitosis/ea7047138b23bc737059fb1e1d581422 to your computer and use it in GitHub Desktop.
Save cellularmitosis/ea7047138b23bc737059fb1e1d581422 to your computer and use it in GitHub Desktop.
Zener+BJT constant current sinks and sources

Blog 2020/10/2

<- previous | index | next ->

Zener+BJT constant current sinks and sources

A basic constant-current source or sink can be constructed from a Zener, a BJT, and a few resistors.

Because it is easy to forget the particular arrangement of the parts for each of the four configurations, I've enumerated each of them below.

In each LTspice simulation, the voltage source is 12V +/- 1V @ 60Hz, which approximates a rectified and filtered but unregulated voltage rail.

Each screenshot actually shows three simulations, where Rload is 4.7, 10 and 22 Ohms. This is difficult to see because the graphs are right on top of each other (indicating that the current regulation is independent of the load resistor value).

The current regulation performance isn't spectacular, because the Zener's voltage regulation isn't perfect. These circuits are useful as a conceptual base to start from, but could be improved upon, perhaps with cascaded Zener shunt regulators, or by replacing Rz with a JFET.

Positive constant-current source

Screenshot_2020-10-02_19-40-50

Positive constant-current sink

Screenshot_2020-10-02_19-43-19

Negative constant-current source

Screenshot_2020-10-02_19-38-23

Negative constant-current sink

Screenshot_2020-10-02_19-33-24

Version 4
SHEET 1 1000 680
WIRE -48 -240 -160 -240
WIRE 224 -240 -48 -240
WIRE 448 -240 224 -240
WIRE 624 -240 448 -240
WIRE -160 -208 -160 -240
WIRE 448 -176 448 -240
WIRE -48 -128 -48 -240
WIRE 224 -16 224 -240
WIRE 448 48 448 -96
WIRE -48 80 -48 -48
WIRE 224 96 224 64
WIRE 384 96 224 96
WIRE 224 128 224 96
WIRE 448 176 448 144
WIRE -48 304 -48 160
WIRE 224 304 224 192
WIRE 224 304 -48 304
WIRE 448 304 448 256
WIRE 448 304 224 304
FLAG -160 -208 0
SYMBOL zener 240 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 208 -32 R0
SYMATTR InstName Rz
SYMATTR Value 330
SYMBOL voltage -48 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -48 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 60)
SYMBOL res 432 160 R0
SYMATTR InstName Rset
SYMATTR Value 22
SYMBOL npn 384 48 R0
SYMATTR InstName Q2
SYMBOL res 432 -192 R0
SYMATTR InstName Rload
SYMATTR Value {R}
TEXT -108 -286 Left 2 !.tran 0 .1 0 .00001
TEXT 552 72 Left 2 ;constant\ncurrent\nsink
TEXT 192 -288 Left 2 !.step param R list 4.7 10 22
TEXT 248 184 Left 2 ;4.7V
RECTANGLE Normal 128 -32 528 272 2
Version 4
SHEET 1 1000 680
WIRE 224 -240 -64 -240
WIRE 448 -240 224 -240
WIRE 448 -176 448 -240
WIRE -64 -128 -64 -240
WIRE 224 -16 224 -240
WIRE 448 48 448 -96
WIRE -64 80 -64 -48
WIRE 224 96 224 64
WIRE 384 96 224 96
WIRE 224 128 224 96
WIRE 448 176 448 144
WIRE -64 304 -64 160
WIRE -64 304 -112 304
WIRE 224 304 224 192
WIRE 224 304 -64 304
WIRE 448 304 448 256
WIRE 448 304 224 304
WIRE -112 336 -112 304
FLAG -112 336 0
SYMBOL zener 240 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 208 -32 R0
SYMATTR InstName Rz
SYMATTR Value 330
SYMBOL voltage -64 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -64 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 60)
SYMBOL res 432 160 R0
SYMATTR InstName Rset
SYMATTR Value 22
SYMBOL npn 384 48 R0
SYMATTR InstName Q2
SYMBOL res 432 -192 R0
SYMATTR InstName Rload
SYMATTR Value {R}
TEXT -112 -288 Left 2 !.tran 0 .1 0 .00001
TEXT 552 72 Left 2 ;constant\ncurrent\nsink
TEXT 192 -288 Left 2 !.step param R list 4.7 10 22
TEXT 248 184 Left 2 ;4.7V
RECTANGLE Normal 128 -32 528 272 2
Version 4
SHEET 1 1000 680
WIRE -48 -240 -160 -240
WIRE 224 -240 -48 -240
WIRE 448 -240 224 -240
WIRE 624 -240 448 -240
WIRE -160 -208 -160 -240
WIRE 448 -192 448 -240
WIRE 224 -144 224 -240
WIRE -48 -128 -48 -240
WIRE 448 -80 448 -112
WIRE 224 -32 224 -80
WIRE 384 -32 224 -32
WIRE 224 0 224 -32
WIRE -48 80 -48 -48
WIRE 448 160 448 16
WIRE -48 304 -48 160
WIRE 224 304 224 80
WIRE 224 304 -48 304
WIRE 448 304 448 240
WIRE 448 304 224 304
FLAG -160 -208 0
SYMBOL zener 240 -80 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 208 -16 R0
SYMATTR InstName Rz
SYMATTR Value 330
SYMBOL voltage -48 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -48 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 60)
SYMBOL res 432 -208 R0
SYMATTR InstName Rset
SYMATTR Value 22
SYMBOL res 432 144 R0
SYMATTR InstName Rload
SYMATTR Value {R}
SYMBOL pnp 384 16 M180
SYMATTR InstName Q1
TEXT -108 -286 Left 2 !.tran 0 .1 0 .00001
TEXT 552 -88 Left 2 ;constant\ncurrent\nsource
TEXT 192 -288 Left 2 !.step param R list 4.7 10 22
TEXT 256 -112 Left 2 ;4.7V
RECTANGLE Normal 128 -208 528 96 2
Version 4
SHEET 1 1000 680
WIRE 224 -240 -80 -240
WIRE 448 -240 224 -240
WIRE 448 -192 448 -240
WIRE 224 -144 224 -240
WIRE -80 -128 -80 -240
WIRE 448 -80 448 -112
WIRE 224 -32 224 -80
WIRE 384 -32 224 -32
WIRE 224 0 224 -32
WIRE -80 80 -80 -48
WIRE 448 160 448 16
WIRE -80 304 -80 160
WIRE -80 304 -128 304
WIRE 224 304 224 80
WIRE 224 304 -80 304
WIRE 448 304 448 240
WIRE 448 304 224 304
WIRE -128 336 -128 304
FLAG -128 336 0
SYMBOL zener 240 -80 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 208 -16 R0
SYMATTR InstName Rz
SYMATTR Value 330
SYMBOL voltage -80 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -80 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 60)
SYMBOL res 432 -208 R0
SYMATTR InstName Rset
SYMATTR Value 22
SYMBOL res 432 144 R0
SYMATTR InstName Rload
SYMATTR Value {R}
SYMBOL pnp 384 16 M180
SYMATTR InstName Q1
TEXT -108 -286 Left 2 !.tran 0 .1 0 .00001
TEXT 552 -88 Left 2 ;constant\ncurrent\nsource
TEXT 192 -288 Left 2 !.step param R list 4.7 10 22
TEXT 256 -112 Left 2 ;4.7V
RECTANGLE Normal 128 -208 528 96 2
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment