cfelton

from random import randint
from myhdl import *

class MemPort:
    def __init__(self,depth=128):
        self.addr = Signal(modbv(0, min=0, max=depth))
        self.wdata = Signal(intbv(0)[8:])
        self.we = Signal(bool(0))
        self.rdata = Signal(intbv(0)[8:])
    def get_signals(self):

cfelton

from myhdl import *

def top(sda, scl, sda_i, sda_o, scl_i, scl_o):
     """Simple I2C bi-dir converter.
     This example will break the I2C bi-directional signals into
     uni-dir explicit signals.
     """
     sda_d = sda.driver()
     scl_d = scl.driver()

cfelton

fsm.act(fsm.REGULAR,If(self.refresh_req,fsm.next_state(fsm.REFRESH)).Elif(cmdsource.stb,
    If(has_openrow, If(hit,
			# NB: write-to-read specification is enforced by multiplexer
			self.cmd.stb.eq(1),cmdsource.ack.eq(self.cmd.ack),self.cmd.is_read.eq(~cmdsource.we),
			self.cmd.is_write.eq(cmdsource.we),self.cmd.cas_n.eq(0),
			self.cmd.we_n.eq(~cmdsource.we)).Else(fsm.next_state(fsm.PRECHARGE))
		      ).Else(fsm.next_state(fsm.ACTIVATE))))

cfelton

from myhdl import *

def simple_add(a,b,):
    c = a + b
    return c

def top(clock,reset,a,b,c):
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        c.next = simple_add(a,b)

cfelton

#
#
# ISE implementation script
# create: Mon, 02 Dec 2013 14:33:07 +0000
# by: ex_xula.py
#
#
# set compile directory:
set compile_directory .
set top_name xula

cfelton

from myhdl import *

# counter with assign
def m_counter(i_clk, i_reset, o_count):
    #s_count = Signal(modbv(0, min=0, max=256))
    @always_seq(i_clk.posedge, reset=i_reset)
    def rtl_count():
        o_count.next = o_count + 1

    # following doesnt' convert with 0.8.1, sims ok

cfelton

from __future__ import division
from __future__ import print_function

from myhdl import *

# my module
def m_add(clock, reset, x, y, z):
    """ y = x + 1, z = x + 3
    """
    @always_seq(clock.posedge, reset=reset)

cfelton

from random import randint
from myhdl import *

def m_random_assign(clock, reset, xb):
    Xc = randint(0, 1)
    print(type(xb), xb)
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        xb.next = Xc
    return rtl

cfelton

from copy import copy
from myhdl import *

def m_mdarray_top(clock, reset, x, y):
    N = 16
    M = 5
    A = [[Signal(intbv(0)[8:]) for _ in range(N)]
         for __ in range(M)]
    B = copy(A)
    g = m_mdarray(clock, reset, A, B, N, M)

cfelton

from myhdl import *
import myhdl_tools as mt

def m_add(a, b, c):
    @always_comb
    def rtl():
        c.next = a and b
    return rtl

def test():