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@ebarlas
ebarlas / Bench.java
Last active September 19, 2023 03:11
Page Extraction for Pagination in Java - Sort vs Heap vs Heapify
package bench;
import java.util.ArrayList;
import java.util.Comparator;
import java.util.IntSummaryStatistics;
import java.util.List;
import java.util.PriorityQueue;
import java.util.Random;
import java.util.stream.IntStream;
@StephanTLavavej
StephanTLavavej / videos.md
Last active October 28, 2025 14:56
C++ Videos by Stephan T. Lavavej

C9 Lectures

BoostCon (now known as C++Now)

  • 2009: I am not aware of recordings for my talks "C++0x Support in Visual Studio 2010" and "The Parallel Patterns Library in Visual Studio 2010". You aren't missing anything, though.
  • 2010: "Data Structure Visualizers in Visual Studio 2010" is irrelevant as the old visualizer machinery has been completely replaced by something much better (and documented).
  • 2012: Regex In C++11 And Boost
@pervognsen
pervognsen / shift_dfa.md
Last active September 19, 2025 07:53
Shift-based DFAs

A traditional table-based DFA implementation looks like this:

uint8_t table[NUM_STATES][256]

uint8_t run(const uint8_t *start, const uint8_t *end, uint8_t state) {
    for (const uint8_t *s = start; s != end; s++)
        state = table[state][*s];
    return state;
}

User authentication system

Your task is now to create a user authentication system.

This document will guide you through all the features and implication of such system, so that you don't have to search them yourself.

We will focus on web/browser-technologies, however similar concept can be widely applied. This guide, is a work in progress, feel free to comment and provide feedbacks.

Expected Workflows

Foreward

This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.

It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.

Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2

Original Foreword: Some Opinion

The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and

@johnmcfarlane
johnmcfarlane / begin(C++).md
Last active October 17, 2025 19:58
Resources for C++ beginners