davilamds

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparadorvhdl is
    Port ( eq : out  STD_LOGIC;
           A : in  STD_LOGIC;
           B : in  STD_LOGIC);
end comparadorvhdl;

architecture sop_arch of comparadorvhdl is

davilamds

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity eq2 is
    
    Port ( a : in  STD_LOGIC_VECTOR (1 downto 0);
	   b : in  STD_LOGIC_VECTOR (1 downto 0);
	   aeqb: out STD_LOGIC);
 
end eq2;

davilamds

library ieee;
use ieee.std_logic_1164.all;
entity eq2_testbench is
end eq2_testbench;
architecture tb_arch of eq2_testbench is

  signal test_in0 , test_in1 : std_logic_vector (1 downto 0);
  signal test_out : std_logic;
begin
  uut : entity work.eq2(struc_arch)

davilamds

library ieee;
use ieee.std_logic_1164.all;
entity eq1 is
port(
     i0 , i1: in std_logic;
     eq: out std_logic);
end eq1;
 
architecture sop_arch of eq1 is
     signal p0 , p1 : std_logic;

davilamds

/* 
 * File:   hmheader.h
 * Author: MIGUEL
 *
 * Created on 9 de julio de 2014, 10:07 p.m.
 */


// PIC16F628A Configuration Bit Settings

davilamds

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Priority_encoder is

port(
	r: in std_logic_vector(4 downto 1);
	pcode: out std_logic_vector(2 downto 0)
);
end Priority_encoder;

davilamds

NET "r<4>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "r<3>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "r<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "r<1>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "pcode<2>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "pcode<1>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "pcode<0>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

davilamds

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY encoderp_sym IS
END encoderp_sym;
 
ARCHITECTURE tb_arch OF encoderp_sym IS 
 
	signal test_r: std_logic_vector(4 downto 1);
	signal test_pcode: std_logic_vector(2 downto 0);

davilamds

/* 
 * File:   serialasincrono.c
 * Author: MIGUEL
 *
 * Created on 3 de septiembre de 2014, 10:07 p.m.
 *
 * Programa: Transmite las letras H,O,L,A en modo asíncrono 9600/8N1
 */

#include <stdio.h>

davilamds

module comparador1bit_verilog(
	//declaración de entradas y salidas
	input wire A, B;
	output wire eq
);
	//declaración de señales internas
	wire p0, p1;

	//comportamiento del módulo
	assign eq= p0 | p1;