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nickfox-taterli / wsram.v
Created April 2, 2024 14:13
wishbone sram
module top(
input [31:0] adr,
input [31:0] dat_w,
output reg [31:0] dat_r,
input [3:0] sel,
input cyc,
input stb,
output reg ack,
input we,
input [2:0] cti,
@nickfox-taterli
nickfox-taterli / spi.v
Created March 23, 2024 13:39
spi slave at tang nano 20k
module top(
input wire clk_i,
input wire rst_i,
input wire sdi_csn_i,
input wire sdi_clk_i,
input wire sdi_dat_i,
output wire sdi_dat_o,
output wire [5:0] led
@nickfox-taterli
nickfox-taterli / bram_axil.v
Last active February 15, 2024 14:01
bram_axil.v
module bram_axil(
input wire clk,
input wire rst,
input wire [31:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvaild,
output wire s_axil_awready,
input wire [31:0] s_axil_wdata,
input wire [3:0] s_axil_wstrb,
@nickfox-taterli
nickfox-taterli / ser_10to1.v
Created January 11, 2024 09:03
Zynq HDMI Output
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/01/08 18:22:57
// Design Name:
// Module Name: ser_10to1
// Project Name:
// Target Devices:
@nickfox-taterli
nickfox-taterli / fsm.v
Created October 19, 2023 10:12
fsm.py to fsm.v - migen default
/* Machine-generated using Migen */
module top(
output reg example,
output reg [7:0] example_1,
output fsm,
output reg fsm_1,
output fsm_2,
output reg fsm_3,
input sys_clk,
input sys_rst
@nickfox-taterli
nickfox-taterli / qmtech_ep4cgx150.v
Created October 13, 2023 11:45
Qmtech EP4CGX150 VexRiscv by Litex Tools
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : qmtech_ep4cgx150.v
// Device : EP4CGX150DF27I7
@nickfox-taterli
nickfox-taterli / CLineGraphDraw.php
Created August 12, 2023 10:21
Zabbix Big Font size
<?php
/*
** Zabbix
** Copyright (C) 2001-2023 Zabbix SIA
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
@nickfox-taterli
nickfox-taterli / top.v
Created August 2, 2023 03:49
flash_led.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/08/01 22:34:37
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
@nickfox-taterli
nickfox-taterli / 免流.md
Created April 24, 2023 08:16
免流记录

关于免流和混淆

一、什么是免流?

答:通过混淆协议的方式伪装正常使用的流量到套餐卡免费流量访问范围内,以此做到欺骗运营商,达到薅运营商羊毛的手段,并且部分卡和地区还可以突破无限流量(实际到某流量量限速到3G/2G)卡限速。

二、怎么样免流?

答:通过混淆协议的方式。例如SSR提供的混淆协议功能。

@nickfox-taterli
nickfox-taterli / FLASH_Test.c
Created April 17, 2023 14:26
CH32V003 FLASH Test
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.