cfelton

"""
      Registers are on 32bit boundaries and are big-edian.  Meaning
      the most significant byte is byte 0.  Example the first register
      byte addresses are:
        LSB 3 byte == address 0x63
            2 byte == address 0x62
            1 byte == address 0x61
        MSB 0 byte == address 0x60

      Registers: (Base address +)

cfelton

def VHDL_ENTITY(clock, reset, x, y, z):
    z.driven = True
    @always(clock, reset, x, y)
    def logic():
        pass
    return logic
VHDL_ENTITY.vhdl_instance = "VHDL_INSTANCE_NAME"

def m_top(clock, reset, x, y, z):
    g = VHDL_ENTITY(clock, reset, x, y, z)

cfelton

--**********************************************************************
-- Copyright (c) 1997-2014 by XESS Corp <http://www.xess.com>.
-- All rights reserved.
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3.0 of the License, or (at your option) any later version.
-- 
-- This library is distributed in the hope that it will be useful,

cfelton

from myhdl import *

class Mux(object):
    def __init__(self, inputs, output, sel):
        self.nports = len(inputs)
        self.inputs = inputs
        self.output = output
        self.sel = sel
        

cfelton

#!/bin/env python
 
from myhdl import *
 
class RegFile(object):
    def __init__(self):
        # actual memory storage
        self._mem   = [Signal(intbv(0)[8:]) for i in xrange(20)]
 
        # named registers port for reading

cfelton

from datetime import datetime
dtnow = datetime.now
from pprint import pprint

from myhdl import *
import gizflo as gf

def m_pe(clock, x, y, z, zu, zl, a=2, b=4):
    

cfelton

import myhdl
print(myhdl.__version__)
from myhdl import *

#------------------------------------------------------------------------
def m_shadow_bittest(clock, sdi, sdo):
    """
    This module demostrates a ShadowSignal (slice) of an element
    in a list-of-signals is converted as a constant
    """

cfelton

    def WriteVidPid(self, vid, pid, addr=0xA0):

        try:
            vid_lo = vid & 0xFF
            vid_hi = (vid >> 8) & 0xFF
            pid_lo = pid & 0xFF
            pid_hi = (pid >> 8) & 0xFF
            
            ControlBuffer = c_ubyte * 16
            d = ControlBuffer()

cfelton

def m_flatten(matrix, flat):
    _flat = ConcatSignal(*[col(4,0) for row in matrix for col in row])
    @always_comb
    def rtl():
        flat.next = _flat
    return rtl


def test_flatten():
    matrix = [[Signal(intbv(0)[8:]) for col in range(5)] for row in range(8)]    

cfelton

from __future__ import print_function

from random import randint
from myhdl import *

def m_top_const(clock, reset, x, y, a, b, N=10):
    # a tuple of constant ints
    coef = tuple([(randint(-19,23), randint(0,127),) 
                 for _ in range(N)])