cfelton

from __future__ import division
from __future__ import print_function

from myhdl import *

# my module
def m_add(clock, reset, x, y, z):
    """ y = x + 1, z = x + 3
    """
    @always_seq(clock.posedge, reset=reset)

cfelton

from random import randint
from myhdl import *

def m_random_assign(clock, reset, xb):
    Xc = randint(0, 1)
    print(type(xb), xb)
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        xb.next = Xc
    return rtl

cfelton

from copy import copy
from myhdl import *

def m_mdarray_top(clock, reset, x, y):
    N = 16
    M = 5
    A = [[Signal(intbv(0)[8:]) for _ in range(N)]
         for __ in range(M)]
    B = copy(A)
    g = m_mdarray(clock, reset, A, B, N, M)

cfelton

from myhdl import *
import myhdl_tools as mt

def m_add(a, b, c):
    @always_comb
    def rtl():
        c.next = a and b
    return rtl

def test():

cfelton

"""
      Registers are on 32bit boundaries and are big-edian.  Meaning
      the most significant byte is byte 0.  Example the first register
      byte addresses are:
        LSB 3 byte == address 0x63
            2 byte == address 0x62
            1 byte == address 0x61
        MSB 0 byte == address 0x60

      Registers: (Base address +)

cfelton

def VHDL_ENTITY(clock, reset, x, y, z):
    z.driven = True
    @always(clock, reset, x, y)
    def logic():
        pass
    return logic
VHDL_ENTITY.vhdl_instance = "VHDL_INSTANCE_NAME"

def m_top(clock, reset, x, y, z):
    g = VHDL_ENTITY(clock, reset, x, y, z)

cfelton

from myhdl import *

class Mux(object):
    def __init__(self, inputs, output, sel):
        self.nports = len(inputs)
        self.inputs = inputs
        self.output = output
        self.sel = sel
        

cfelton

#!/bin/env python
 
from myhdl import *
 
class RegFile(object):
    def __init__(self):
        # actual memory storage
        self._mem   = [Signal(intbv(0)[8:]) for i in xrange(20)]
 
        # named registers port for reading

cfelton

from datetime import datetime
dtnow = datetime.now
from pprint import pprint

from myhdl import *
import gizflo as gf

def m_pe(clock, x, y, z, zu, zl, a=2, b=4):
    

cfelton

import myhdl
print(myhdl.__version__)
from myhdl import *

#------------------------------------------------------------------------
def m_shadow_bittest(clock, sdi, sdo):
    """
    This module demostrates a ShadowSignal (slice) of an element
    in a list-of-signals is converted as a constant
    """