gibiansky

// Our input and output signals are all one bit.
// We could make them more than one bit; the only
// thing that would change is we would have to write
//  e.g "input [0:N] a" instead of "input a".
module mux(input a, input b, input select, output out);
    // Verilog code goes here
endmodule

gibiansky

module mux(input a, input b, input select, output out);
  assign out = select ? a : b;
endmodule

gibiansky

module mux_test;

reg a, b, s;
wire out;

mux my_mux(a, b, s, out);

initial begin
    a <= 0;
    b <= 1;

gibiansky

reg a, b, s;
wire out;

gibiansky

mux my_mux(a, b, s, out); 

gibiansky

initial begin
    // Simulation code
end

gibiansky

a <= 0;
b <= 1;
s <= 0; 

gibiansky

#1;
$display("In: %b, %b select %b. Out %b.", a, b, s, out);
#1; 

gibiansky

module fib(input clock, reset, input [5:0] n, output ready, output [31:0] value)
// Computational circuit
endmodule

gibiansky

module fib(input clock, reset, input [5:0] n, output ready, output [31:0] value)

reg [31:0] previous, current;
reg [5:0] counter;

always @(posedge reset)
    begin
        previous <= 32'd0;
        current <= 32'd1;
        counter <= 32'd1;